cranelift_codegen::isa::aarch64::inst

Enum Inst

Source 
pub enum Inst {

Show 137 variants    Nop0,
    Nop4,
    AluRRR {
        alu_op: ALUOp,
        size: OperandSize,
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
    },
    AluRRRR {
        alu_op: ALUOp3,
        size: OperandSize,
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
        ra: Reg,
    },
    AluRRImm12 {
        alu_op: ALUOp,
        size: OperandSize,
        rd: Writable<Reg>,
        rn: Reg,
        imm12: Imm12,
    },
    AluRRImmLogic {
        alu_op: ALUOp,
        size: OperandSize,
        rd: Writable<Reg>,
        rn: Reg,
        imml: ImmLogic,
    },
    AluRRImmShift {
        alu_op: ALUOp,
        size: OperandSize,
        rd: Writable<Reg>,
        rn: Reg,
        immshift: ImmShift,
    },
    AluRRRShift {
        alu_op: ALUOp,
        size: OperandSize,
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
        shiftop: ShiftOpAndAmt,
    },
    AluRRRExtend {
        alu_op: ALUOp,
        size: OperandSize,
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
        extendop: ExtendOp,
    },
    BitRR {
        op: BitOp,
        size: OperandSize,
        rd: Writable<Reg>,
        rn: Reg,
    },
    ULoad8 {
        rd: Writable<Reg>,
        mem: AMode,
        flags: MemFlags,
    },
    SLoad8 {
        rd: Writable<Reg>,
        mem: AMode,
        flags: MemFlags,
    },
    ULoad16 {
        rd: Writable<Reg>,
        mem: AMode,
        flags: MemFlags,
    },
    SLoad16 {
        rd: Writable<Reg>,
        mem: AMode,
        flags: MemFlags,
    },
    ULoad32 {
        rd: Writable<Reg>,
        mem: AMode,
        flags: MemFlags,
    },
    SLoad32 {
        rd: Writable<Reg>,
        mem: AMode,
        flags: MemFlags,
    },
    ULoad64 {
        rd: Writable<Reg>,
        mem: AMode,
        flags: MemFlags,
    },
    Store8 {
        rd: Reg,
        mem: AMode,
        flags: MemFlags,
    },
    Store16 {
        rd: Reg,
        mem: AMode,
        flags: MemFlags,
    },
    Store32 {
        rd: Reg,
        mem: AMode,
        flags: MemFlags,
    },
    Store64 {
        rd: Reg,
        mem: AMode,
        flags: MemFlags,
    },
    StoreP64 {
        rt: Reg,
        rt2: Reg,
        mem: PairAMode,
        flags: MemFlags,
    },
    LoadP64 {
        rt: Writable<Reg>,
        rt2: Writable<Reg>,
        mem: PairAMode,
        flags: MemFlags,
    },
    Mov {
        size: OperandSize,
        rd: Writable<Reg>,
        rm: Reg,
    },
    MovFromPReg {
        rd: Writable<Reg>,
        rm: PReg,
    },
    MovToPReg {
        rd: PReg,
        rm: Reg,
    },
    MovWide {
        op: MoveWideOp,
        rd: Writable<Reg>,
        imm: MoveWideConst,
        size: OperandSize,
    },
    MovK {
        rd: Writable<Reg>,
        rn: Reg,
        imm: MoveWideConst,
        size: OperandSize,
    },
    Extend {
        rd: Writable<Reg>,
        rn: Reg,
        signed: bool,
        from_bits: u8,
        to_bits: u8,
    },
    CSel {
        rd: Writable<Reg>,
        cond: Cond,
        rn: Reg,
        rm: Reg,
    },
    CSNeg {
        rd: Writable<Reg>,
        cond: Cond,
        rn: Reg,
        rm: Reg,
    },
    CSet {
        rd: Writable<Reg>,
        cond: Cond,
    },
    CSetm {
        rd: Writable<Reg>,
        cond: Cond,
    },
    CCmp {
        size: OperandSize,
        rn: Reg,
        rm: Reg,
        nzcv: NZCV,
        cond: Cond,
    },
    CCmpImm {
        size: OperandSize,
        rn: Reg,
        imm: UImm5,
        nzcv: NZCV,
        cond: Cond,
    },
    AtomicRMWLoop {
        ty: Type,
        op: AtomicRMWLoopOp,
        flags: MemFlags,
        addr: Reg,
        operand: Reg,
        oldval: Writable<Reg>,
        scratch1: Writable<Reg>,
        scratch2: Writable<Reg>,
    },
    AtomicCASLoop {
        ty: Type,
        flags: MemFlags,
        addr: Reg,
        expected: Reg,
        replacement: Reg,
        oldval: Writable<Reg>,
        scratch: Writable<Reg>,
    },
    AtomicRMW {
        op: AtomicRMWOp,
        rs: Reg,
        rt: Writable<Reg>,
        rn: Reg,
        ty: Type,
        flags: MemFlags,
    },
    AtomicCAS {
        rd: Writable<Reg>,
        rs: Reg,
        rt: Reg,
        rn: Reg,
        ty: Type,
        flags: MemFlags,
    },
    LoadAcquire {
        access_ty: Type,
        rt: Writable<Reg>,
        rn: Reg,
        flags: MemFlags,
    },
    StoreRelease {
        access_ty: Type,
        rt: Reg,
        rn: Reg,
        flags: MemFlags,
    },
    Fence,
    Csdb,
    FpuMove32 {
        rd: Writable<Reg>,
        rn: Reg,
    },
    FpuMove64 {
        rd: Writable<Reg>,
        rn: Reg,
    },
    FpuMove128 {
        rd: Writable<Reg>,
        rn: Reg,
    },
    FpuMoveFromVec {
        rd: Writable<Reg>,
        rn: Reg,
        idx: u8,
        size: VectorSize,
    },
    FpuExtend {
        rd: Writable<Reg>,
        rn: Reg,
        size: ScalarSize,
    },
    FpuRR {
        fpu_op: FPUOp1,
        size: ScalarSize,
        rd: Writable<Reg>,
        rn: Reg,
    },
    FpuRRR {
        fpu_op: FPUOp2,
        size: ScalarSize,
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
    },
    FpuRRI {
        fpu_op: FPUOpRI,
        rd: Writable<Reg>,
        rn: Reg,
    },
    FpuRRIMod {
        fpu_op: FPUOpRIMod,
        rd: Writable<Reg>,
        ri: Reg,
        rn: Reg,
    },
    FpuRRRR {
        fpu_op: FPUOp3,
        size: ScalarSize,
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
        ra: Reg,
    },
    FpuCmp {
        size: ScalarSize,
        rn: Reg,
        rm: Reg,
    },
    FpuLoad16 {
        rd: Writable<Reg>,
        mem: AMode,
        flags: MemFlags,
    },
    FpuStore16 {
        rd: Reg,
        mem: AMode,
        flags: MemFlags,
    },
    FpuLoad32 {
        rd: Writable<Reg>,
        mem: AMode,
        flags: MemFlags,
    },
    FpuStore32 {
        rd: Reg,
        mem: AMode,
        flags: MemFlags,
    },
    FpuLoad64 {
        rd: Writable<Reg>,
        mem: AMode,
        flags: MemFlags,
    },
    FpuStore64 {
        rd: Reg,
        mem: AMode,
        flags: MemFlags,
    },
    FpuLoad128 {
        rd: Writable<Reg>,
        mem: AMode,
        flags: MemFlags,
    },
    FpuStore128 {
        rd: Reg,
        mem: AMode,
        flags: MemFlags,
    },
    FpuLoadP64 {
        rt: Writable<Reg>,
        rt2: Writable<Reg>,
        mem: PairAMode,
        flags: MemFlags,
    },
    FpuStoreP64 {
        rt: Reg,
        rt2: Reg,
        mem: PairAMode,
        flags: MemFlags,
    },
    FpuLoadP128 {
        rt: Writable<Reg>,
        rt2: Writable<Reg>,
        mem: PairAMode,
        flags: MemFlags,
    },
    FpuStoreP128 {
        rt: Reg,
        rt2: Reg,
        mem: PairAMode,
        flags: MemFlags,
    },
    FpuToInt {
        op: FpuToIntOp,
        rd: Writable<Reg>,
        rn: Reg,
    },
    IntToFpu {
        op: IntToFpuOp,
        rd: Writable<Reg>,
        rn: Reg,
    },
    FpuCSel16 {
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
        cond: Cond,
    },
    FpuCSel32 {
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
        cond: Cond,
    },
    FpuCSel64 {
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
        cond: Cond,
    },
    FpuRound {
        op: FpuRoundMode,
        rd: Writable<Reg>,
        rn: Reg,
    },
    MovToFpu {
        rd: Writable<Reg>,
        rn: Reg,
        size: ScalarSize,
    },
    FpuMoveFPImm {
        rd: Writable<Reg>,
        imm: ASIMDFPModImm,
        size: ScalarSize,
    },
    MovToVec {
        rd: Writable<Reg>,
        ri: Reg,
        rn: Reg,
        idx: u8,
        size: VectorSize,
    },
    MovFromVec {
        rd: Writable<Reg>,
        rn: Reg,
        idx: u8,
        size: ScalarSize,
    },
    MovFromVecSigned {
        rd: Writable<Reg>,
        rn: Reg,
        idx: u8,
        size: VectorSize,
        scalar_size: OperandSize,
    },
    VecDup {
        rd: Writable<Reg>,
        rn: Reg,
        size: VectorSize,
    },
    VecDupFromFpu {
        rd: Writable<Reg>,
        rn: Reg,
        size: VectorSize,
        lane: u8,
    },
    VecDupFPImm {
        rd: Writable<Reg>,
        imm: ASIMDFPModImm,
        size: VectorSize,
    },
    VecDupImm {
        rd: Writable<Reg>,
        imm: ASIMDMovModImm,
        invert: bool,
        size: VectorSize,
    },
    VecExtend {
        t: VecExtendOp,
        rd: Writable<Reg>,
        rn: Reg,
        high_half: bool,
        lane_size: ScalarSize,
    },
    VecMovElement {
        rd: Writable<Reg>,
        ri: Reg,
        rn: Reg,
        dest_idx: u8,
        src_idx: u8,
        size: VectorSize,
    },
    VecRRLong {
        op: VecRRLongOp,
        rd: Writable<Reg>,
        rn: Reg,
        high_half: bool,
    },
    VecRRNarrowLow {
        op: VecRRNarrowOp,
        rd: Writable<Reg>,
        rn: Reg,
        lane_size: ScalarSize,
    },
    VecRRNarrowHigh {
        op: VecRRNarrowOp,
        rd: Writable<Reg>,
        ri: Reg,
        rn: Reg,
        lane_size: ScalarSize,
    },
    VecRRPair {
        op: VecPairOp,
        rd: Writable<Reg>,
        rn: Reg,
    },
    VecRRRLong {
        alu_op: VecRRRLongOp,
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
        high_half: bool,
    },
    VecRRRLongMod {
        alu_op: VecRRRLongModOp,
        rd: Writable<Reg>,
        ri: Reg,
        rn: Reg,
        rm: Reg,
        high_half: bool,
    },
    VecRRPairLong {
        op: VecRRPairLongOp,
        rd: Writable<Reg>,
        rn: Reg,
    },
    VecRRR {
        alu_op: VecALUOp,
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
        size: VectorSize,
    },
    VecRRRMod {
        alu_op: VecALUModOp,
        rd: Writable<Reg>,
        ri: Reg,
        rn: Reg,
        rm: Reg,
        size: VectorSize,
    },
    VecFmlaElem {
        alu_op: VecALUModOp,
        rd: Writable<Reg>,
        ri: Reg,
        rn: Reg,
        rm: Reg,
        size: VectorSize,
        idx: u8,
    },
    VecMisc {
        op: VecMisc2,
        rd: Writable<Reg>,
        rn: Reg,
        size: VectorSize,
    },
    VecLanes {
        op: VecLanesOp,
        rd: Writable<Reg>,
        rn: Reg,
        size: VectorSize,
    },
    VecShiftImm {
        op: VecShiftImmOp,
        rd: Writable<Reg>,
        rn: Reg,
        size: VectorSize,
        imm: u8,
    },
    VecShiftImmMod {
        op: VecShiftImmModOp,
        rd: Writable<Reg>,
        ri: Reg,
        rn: Reg,
        size: VectorSize,
        imm: u8,
    },
    VecExtract {
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
        imm4: u8,
    },
    VecTbl {
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
    },
    VecTblExt {
        rd: Writable<Reg>,
        ri: Reg,
        rn: Reg,
        rm: Reg,
    },
    VecTbl2 {
        rd: Writable<Reg>,
        rn: Reg,
        rn2: Reg,
        rm: Reg,
    },
    VecTbl2Ext {
        rd: Writable<Reg>,
        ri: Reg,
        rn: Reg,
        rn2: Reg,
        rm: Reg,
    },
    VecLoadReplicate {
        rd: Writable<Reg>,
        rn: Reg,
        size: VectorSize,
        flags: MemFlags,
    },
    VecCSel {
        rd: Writable<Reg>,
        rn: Reg,
        rm: Reg,
        cond: Cond,
    },
    MovToNZCV {
        rn: Reg,
    },
    MovFromNZCV {
        rd: Writable<Reg>,
    },
    Call {
        info: Box<CallInfo<ExternalName>>,
    },
    CallInd {
        info: Box<CallInfo<Reg>>,
    },
    ReturnCall {
        info: Box<ReturnCallInfo<ExternalName>>,
    },
    ReturnCallInd {
        info: Box<ReturnCallInfo<Reg>>,
    },
    Args {
        args: Vec<ArgPair>,
    },
    Rets {
        rets: Vec<RetPair>,
    },
    Ret,
    AuthenticatedRet {
        key: APIKey,
        is_hint: bool,
    },
    Jump {
        dest: BranchTarget,
    },
    CondBr {
        taken: BranchTarget,
        not_taken: BranchTarget,
        kind: CondBrKind,
    },
    TestBitAndBranch {
        kind: TestBitAndBranchKind,
        taken: BranchTarget,
        not_taken: BranchTarget,
        rn: Reg,
        bit: u8,
    },
    TrapIf {
        kind: CondBrKind,
        trap_code: TrapCode,
    },
    IndirectBr {
        rn: Reg,
        targets: Vec<MachLabel>,
    },
    Brk,
    Udf {
        trap_code: TrapCode,
    },
    Adr {
        rd: Writable<Reg>,
        off: i32,
    },
    Adrp {
        rd: Writable<Reg>,
        off: i32,
    },
    Word4 {
        data: u32,
    },
    Word8 {
        data: u64,
    },
    JTSequence {
        default: MachLabel,
        targets: Box<Vec<MachLabel>>,
        ridx: Reg,
        rtmp1: Writable<Reg>,
        rtmp2: Writable<Reg>,
    },
    LoadExtName {
        rd: Writable<Reg>,
        name: Box<ExternalName>,
        offset: i64,
    },
    LoadAddr {
        rd: Writable<Reg>,
        mem: AMode,
    },
    Paci {
        key: APIKey,
    },
    Xpaclri,
    Bti {
        targets: BranchTargetType,
    },
    EmitIsland {
        needed_space: CodeOffset,
    },
    ElfTlsGetAddr {
        symbol: Box<ExternalName>,
        rd: Writable<Reg>,
        tmp: Writable<Reg>,
    },
    MachOTlsGetAddr {
        symbol: ExternalName,
        rd: Writable<Reg>,
    },
    Unwind {
        inst: UnwindInst,
    },
    DummyUse {
        reg: Reg,
    },
    StackProbeLoop {
        start: Writable<Reg>,
        end: Reg,
        step: Imm12,
    },

}
Available on crate feature arm64 only.
Expand description

Internal type MInst: defined at src/isa/aarch64/inst.isle line 1.

Variants§

§

Nop0

§

Nop4

§

AluRRR

Fields

§alu_op: ALUOp
§size: OperandSize
§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§

AluRRRR

Fields

§alu_op: ALUOp3
§size: OperandSize
§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§ra: Reg
§

AluRRImm12

Fields

§alu_op: ALUOp
§size: OperandSize
§rd: Writable<Reg>
§rn: Reg
§imm12: Imm12
§

AluRRImmLogic

Fields

§alu_op: ALUOp
§size: OperandSize
§rd: Writable<Reg>
§rn: Reg
§imml: ImmLogic
§

AluRRImmShift

Fields

§alu_op: ALUOp
§size: OperandSize
§rd: Writable<Reg>
§rn: Reg
§immshift: ImmShift
§

AluRRRShift

Fields

§alu_op: ALUOp
§size: OperandSize
§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§shiftop: ShiftOpAndAmt
§

AluRRRExtend

Fields

§alu_op: ALUOp
§size: OperandSize
§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§extendop: ExtendOp
§

BitRR

Fields

§op: BitOp
§size: OperandSize
§rd: Writable<Reg>
§rn: Reg
§

ULoad8

Fields

§rd: Writable<Reg>
§mem: AMode
§flags: MemFlags
§

SLoad8

Fields

§rd: Writable<Reg>
§mem: AMode
§flags: MemFlags
§

ULoad16

Fields

§rd: Writable<Reg>
§mem: AMode
§flags: MemFlags
§

SLoad16

Fields

§rd: Writable<Reg>
§mem: AMode
§flags: MemFlags
§

ULoad32

Fields

§rd: Writable<Reg>
§mem: AMode
§flags: MemFlags
§

SLoad32

Fields

§rd: Writable<Reg>
§mem: AMode
§flags: MemFlags
§

ULoad64

Fields

§rd: Writable<Reg>
§mem: AMode
§flags: MemFlags
§

Store8

Fields

§rd: Reg
§mem: AMode
§flags: MemFlags
§

Store16

Fields

§rd: Reg
§mem: AMode
§flags: MemFlags
§

Store32

Fields

§rd: Reg
§mem: AMode
§flags: MemFlags
§

Store64

Fields

§rd: Reg
§mem: AMode
§flags: MemFlags
§

StoreP64

Fields

§rt: Reg
§rt2: Reg
§mem: PairAMode
§flags: MemFlags
§

LoadP64

§

Mov

Fields

§size: OperandSize
§rd: Writable<Reg>
§rm: Reg
§

MovFromPReg

Fields

§rd: Writable<Reg>
§rm: PReg
§

MovToPReg

Fields

§rd: PReg
§rm: Reg
§

MovWide

§

MovK

§

Extend

Fields

§rd: Writable<Reg>
§rn: Reg
§signed: bool
§from_bits: u8
§to_bits: u8
§

CSel

Fields

§rd: Writable<Reg>
§cond: Cond
§rn: Reg
§rm: Reg
§

CSNeg

Fields

§rd: Writable<Reg>
§cond: Cond
§rn: Reg
§rm: Reg
§

CSet

Fields

§rd: Writable<Reg>
§cond: Cond
§

CSetm

Fields

§rd: Writable<Reg>
§cond: Cond
§

CCmp

Fields

§size: OperandSize
§rn: Reg
§rm: Reg
§nzcv: NZCV
§cond: Cond
§

CCmpImm

Fields

§size: OperandSize
§rn: Reg
§imm: UImm5
§nzcv: NZCV
§cond: Cond
§

AtomicRMWLoop

Fields

§ty: Type
§op: AtomicRMWLoopOp
§flags: MemFlags
§addr: Reg
§operand: Reg
§oldval: Writable<Reg>
§scratch1: Writable<Reg>
§scratch2: Writable<Reg>
§

AtomicCASLoop

Fields

§ty: Type
§flags: MemFlags
§addr: Reg
§expected: Reg
§replacement: Reg
§oldval: Writable<Reg>
§scratch: Writable<Reg>
§

AtomicRMW

Fields

§op: AtomicRMWOp
§rs: Reg
§rt: Writable<Reg>
§rn: Reg
§ty: Type
§flags: MemFlags
§

AtomicCAS

Fields

§rd: Writable<Reg>
§rs: Reg
§rt: Reg
§rn: Reg
§ty: Type
§flags: MemFlags
§

LoadAcquire

Fields

§access_ty: Type
§rt: Writable<Reg>
§rn: Reg
§flags: MemFlags
§

StoreRelease

Fields

§access_ty: Type
§rt: Reg
§rn: Reg
§flags: MemFlags
§

Fence

§

Csdb

§

FpuMove32

Fields

§rd: Writable<Reg>
§rn: Reg
§

FpuMove64

Fields

§rd: Writable<Reg>
§rn: Reg
§

FpuMove128

Fields

§rd: Writable<Reg>
§rn: Reg
§

FpuMoveFromVec

Fields

§rd: Writable<Reg>
§rn: Reg
§idx: u8
§size: VectorSize
§

FpuExtend

Fields

§rd: Writable<Reg>
§rn: Reg
§size: ScalarSize
§

FpuRR

Fields

§fpu_op: FPUOp1
§size: ScalarSize
§rd: Writable<Reg>
§rn: Reg
§

FpuRRR

Fields

§fpu_op: FPUOp2
§size: ScalarSize
§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§

FpuRRI

Fields

§fpu_op: FPUOpRI
§rd: Writable<Reg>
§rn: Reg
§

FpuRRIMod

Fields

§fpu_op: FPUOpRIMod
§rd: Writable<Reg>
§ri: Reg
§rn: Reg
§

FpuRRRR

Fields

§fpu_op: FPUOp3
§size: ScalarSize
§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§ra: Reg
§

FpuCmp

Fields

§size: ScalarSize
§rn: Reg
§rm: Reg
§

FpuLoad16

Fields

§rd: Writable<Reg>
§mem: AMode
§flags: MemFlags
§

FpuStore16

Fields

§rd: Reg
§mem: AMode
§flags: MemFlags
§

FpuLoad32

Fields

§rd: Writable<Reg>
§mem: AMode
§flags: MemFlags
§

FpuStore32

Fields

§rd: Reg
§mem: AMode
§flags: MemFlags
§

FpuLoad64

Fields

§rd: Writable<Reg>
§mem: AMode
§flags: MemFlags
§

FpuStore64

Fields

§rd: Reg
§mem: AMode
§flags: MemFlags
§

FpuLoad128

Fields

§rd: Writable<Reg>
§mem: AMode
§flags: MemFlags
§

FpuStore128

Fields

§rd: Reg
§mem: AMode
§flags: MemFlags
§

FpuLoadP64

§

FpuStoreP64

Fields

§rt: Reg
§rt2: Reg
§mem: PairAMode
§flags: MemFlags
§

FpuLoadP128

§

FpuStoreP128

Fields

§rt: Reg
§rt2: Reg
§mem: PairAMode
§flags: MemFlags
§

FpuToInt

Fields

§op: FpuToIntOp
§rd: Writable<Reg>
§rn: Reg
§

IntToFpu

Fields

§op: IntToFpuOp
§rd: Writable<Reg>
§rn: Reg
§

FpuCSel16

Fields

§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§cond: Cond
§

FpuCSel32

Fields

§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§cond: Cond
§

FpuCSel64

Fields

§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§cond: Cond
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FpuRound

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MovToFpu

Fields

§rd: Writable<Reg>
§rn: Reg
§size: ScalarSize
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FpuMoveFPImm

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MovToVec

Fields

§rd: Writable<Reg>
§ri: Reg
§rn: Reg
§idx: u8
§size: VectorSize
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MovFromVec

Fields

§rd: Writable<Reg>
§rn: Reg
§idx: u8
§size: ScalarSize
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MovFromVecSigned

Fields

§rd: Writable<Reg>
§rn: Reg
§idx: u8
§size: VectorSize
§scalar_size: OperandSize
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VecDup

Fields

§rd: Writable<Reg>
§rn: Reg
§size: VectorSize
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VecDupFromFpu

Fields

§rd: Writable<Reg>
§rn: Reg
§size: VectorSize
§lane: u8
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VecDupFPImm

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VecDupImm

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VecExtend

Fields

§t: VecExtendOp
§rd: Writable<Reg>
§rn: Reg
§high_half: bool
§lane_size: ScalarSize
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VecMovElement

Fields

§rd: Writable<Reg>
§ri: Reg
§rn: Reg
§dest_idx: u8
§src_idx: u8
§size: VectorSize
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VecRRLong

Fields

§op: VecRRLongOp
§rd: Writable<Reg>
§rn: Reg
§high_half: bool
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VecRRNarrowLow

Fields

§op: VecRRNarrowOp
§rd: Writable<Reg>
§rn: Reg
§lane_size: ScalarSize
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VecRRNarrowHigh

Fields

§op: VecRRNarrowOp
§rd: Writable<Reg>
§ri: Reg
§rn: Reg
§lane_size: ScalarSize
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VecRRPair

Fields

§op: VecPairOp
§rd: Writable<Reg>
§rn: Reg
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VecRRRLong

Fields

§alu_op: VecRRRLongOp
§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§high_half: bool
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VecRRRLongMod

Fields

§alu_op: VecRRRLongModOp
§rd: Writable<Reg>
§ri: Reg
§rn: Reg
§rm: Reg
§high_half: bool
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VecRRPairLong

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VecRRR

Fields

§alu_op: VecALUOp
§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§size: VectorSize
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VecRRRMod

Fields

§alu_op: VecALUModOp
§rd: Writable<Reg>
§ri: Reg
§rn: Reg
§rm: Reg
§size: VectorSize
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VecFmlaElem

Fields

§alu_op: VecALUModOp
§rd: Writable<Reg>
§ri: Reg
§rn: Reg
§rm: Reg
§size: VectorSize
§idx: u8
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VecMisc

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VecLanes

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VecShiftImm

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VecShiftImmMod

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VecExtract

Fields

§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§imm4: u8
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VecTbl

Fields

§rd: Writable<Reg>
§rn: Reg
§rm: Reg
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VecTblExt

Fields

§rd: Writable<Reg>
§ri: Reg
§rn: Reg
§rm: Reg
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VecTbl2

Fields

§rd: Writable<Reg>
§rn: Reg
§rn2: Reg
§rm: Reg
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VecTbl2Ext

Fields

§rd: Writable<Reg>
§ri: Reg
§rn: Reg
§rn2: Reg
§rm: Reg
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VecLoadReplicate

Fields

§rd: Writable<Reg>
§rn: Reg
§size: VectorSize
§flags: MemFlags
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VecCSel

Fields

§rd: Writable<Reg>
§rn: Reg
§rm: Reg
§cond: Cond
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MovToNZCV

Fields

§rn: Reg
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MovFromNZCV

Fields

§rd: Writable<Reg>
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Call

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CallInd

Fields

§info: Box<CallInfo<Reg>>
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ReturnCall

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ReturnCallInd

Fields

§info: Box<ReturnCallInfo<Reg>>
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Args

Fields

§args: Vec<ArgPair>
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Rets

Fields

§rets: Vec<RetPair>
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Ret

§

AuthenticatedRet

Fields

§key: APIKey
§is_hint: bool
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Jump

Fields

§dest: BranchTarget
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CondBr

Fields

§taken: BranchTarget
§not_taken: BranchTarget
§kind: CondBrKind
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TestBitAndBranch

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TrapIf

Fields

§kind: CondBrKind
§trap_code: TrapCode
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IndirectBr

Fields

§rn: Reg
§targets: Vec<MachLabel>
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Brk

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Udf

Fields

§trap_code: TrapCode
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Adr

Fields

§rd: Writable<Reg>
§off: i32
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Adrp

Fields

§rd: Writable<Reg>
§off: i32
§

Word4

Fields

§data: u32
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Word8

Fields

§data: u64
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JTSequence

Fields

§default: MachLabel
§targets: Box<Vec<MachLabel>>
§ridx: Reg
§rtmp1: Writable<Reg>
§rtmp2: Writable<Reg>
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LoadExtName

Fields

§rd: Writable<Reg>
§name: Box<ExternalName>
§offset: i64
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LoadAddr

Fields

§rd: Writable<Reg>
§mem: AMode
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Paci

Fields

§key: APIKey
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Xpaclri

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Bti

Fields

§targets: BranchTargetType
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EmitIsland

Fields

§needed_space: CodeOffset
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ElfTlsGetAddr

Fields

§symbol: Box<ExternalName>
§rd: Writable<Reg>
§tmp: Writable<Reg>
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MachOTlsGetAddr

Fields

§symbol: ExternalName
§rd: Writable<Reg>
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Unwind

Fields

§inst: UnwindInst
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DummyUse

Fields

§reg: Reg
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StackProbeLoop

Fields

§start: Writable<Reg>
§end: Reg
§step: Imm12

Implementations§

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impl Inst

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pub fn load_constant<F: FnMut(Type) -> Writable<Reg>>( rd: Writable<Reg>, value: u64, alloc_tmp: &mut F, ) -> SmallVec<[Inst; 4]>

Create an instruction that loads a constant, using one of several options (MOVZ, MOVN, logical immediate, or constant pool).

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pub fn gen_load( into_reg: Writable<Reg>, mem: AMode, ty: Type, flags: MemFlags, ) -> Inst

Generic constructor for a load (zero-extending where appropriate).

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pub fn gen_store(mem: AMode, from_reg: Reg, ty: Type, flags: MemFlags) -> Inst

Generic constructor for a store.

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pub fn mem_type(&self) -> Option<Type>

What type does this load or store instruction access in memory? When uimm12 encoding is used, the size of this type is the amount that immediate offsets are scaled by.

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impl Clone for MInst

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fn clone(&self) -> MInst

Returns a copy of the value. Read more
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fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Debug for MInst

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl MachInst for Inst

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const TRAP_OPCODE: &'static [u8]

Byte representation of a trap opcode which is inserted by MachBuffer during its defer_trap method.
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type ABIMachineSpec = AArch64MachineDeps

The ABI machine spec for this MachInst.
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type LabelUse = LabelUse

A label-use kind: a type that describes the types of label references that can occur in an instruction.
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fn get_operands(&mut self, collector: &mut impl OperandVisitor)

Return the registers referenced by this machine instruction along with the modes of reference (use, def, modify).
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fn is_move(&self) -> Option<(Writable<Reg>, Reg)>

If this is a simple move, return the (source, destination) tuple of registers.
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fn is_included_in_clobbers(&self) -> bool

Should this instruction be included in the clobber-set?
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fn is_trap(&self) -> bool

Is this an unconditional trap?
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fn is_args(&self) -> bool

Is this an “args” pseudoinst?
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fn is_term(&self) -> MachTerminator

Is this a terminator (branch or ret)? If so, return its type (ret/uncond/cond) and target if applicable.
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fn is_mem_access(&self) -> bool

Does this instruction access memory?
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fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst

Generate a move.
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fn is_safepoint(&self) -> bool

Is this a safepoint?
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fn gen_dummy_use(reg: Reg) -> Inst

Generate a dummy instruction that will keep a value alive but has no other purpose.
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fn gen_nop(preferred_size: usize) -> Inst

Generate a NOP. The preferred_size parameter allows the caller to request a NOP of that size, or as close to it as possible. The machine backend may return a NOP whose binary encoding is smaller than the preferred size, but must not return a NOP that is larger. However, the instruction must have a nonzero size if preferred_size is nonzero.
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fn rc_for_type( ty: Type, ) -> CodegenResult<(&'static [RegClass], &'static [Type])>

Determine register class(es) to store the given Cranelift type, and the Cranelift type actually stored in the underlying register(s). May return an error if the type isn’t supported by this backend. Read more
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fn canonical_type_for_rc(rc: RegClass) -> Type

Get an appropriate type that can fully hold a value in a given register class. This may not be the only type that maps to that class, but when used with gen_move() or the ABI trait’s load/spill constructors, it should produce instruction(s) that move the entire register contents.
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fn gen_jump(target: MachLabel) -> Inst

Generate a jump to another target. Used during lowering of control flow.
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fn worst_case_size() -> CodeOffset

What is the worst-case instruction size emitted by this instruction type?
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fn ref_type_regclass(_: &Flags) -> RegClass

What is the register class used for reference types (GC-observable pointers)? Can be dependent on compilation flags.
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fn gen_block_start( is_indirect_branch_target: bool, is_forward_edge_cfi_enabled: bool, ) -> Option<Self>

Generate an instruction that must appear at the beginning of a basic block, if any. Note that the return value must not be subject to register allocation.
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fn function_alignment() -> FunctionAlignment

Returns a description of the alignment required for functions for this architecture.
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fn gen_imm_u64(_value: u64, _dst: Writable<Reg>) -> Option<Self>

Generate a store of an immediate 64-bit integer to a register. Used by the control plane to generate random instructions.
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fn gen_imm_f64( _value: f64, _tmp: Writable<Reg>, _dst: Writable<Reg>, ) -> SmallVec<[Self; 2]>

Generate a store of an immediate 64-bit integer to a register. Used by the control plane to generate random instructions. The tmp register may be used by architectures which don’t support writing immediate values to floating point registers directly.
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fn align_basic_block(offset: CodeOffset) -> CodeOffset

Align a basic block offset (from start of function). By default, no alignment occurs.
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fn is_low_level_branch(&self) -> bool

Is this a low-level, one-way branch, not meant for use in a VCode body? These instructions are meant to be used only when directly emitted, i.e. when MachInst is used as an assembler library.
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impl MachInstEmit for Inst

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type State = EmitState

Persistent state carried across emit invocations.
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type Info = EmitInfo

Constant information used in emit invocations.
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fn emit( &self, sink: &mut MachBuffer<Inst>, emit_info: &Self::Info, state: &mut EmitState, )

Emit the instruction.
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fn pretty_print_inst(&self, state: &mut Self::State) -> String

Pretty-print the instruction.
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impl MachInstEmitState<MInst> for EmitState

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fn new(abi: &Callee<AArch64MachineDeps>, ctrl_plane: ControlPlane) -> Self

Create a new emission state given the ABI object.
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fn pre_safepoint(&mut self, user_stack_map: Option<UserStackMap>)

Update the emission state before emitting an instruction that is a safepoint.
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fn ctrl_plane_mut(&mut self) -> &mut ControlPlane

The emission state holds ownership of a control plane, so it doesn’t have to be passed around explicitly too much. ctrl_plane_mut may be used if temporary access to the control plane is needed by some other function that doesn’t have access to the emission state.
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fn take_ctrl_plane(self) -> ControlPlane

Used to continue using a control plane after the emission state is not needed anymore.
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fn frame_layout(&self) -> &FrameLayout

The [FrameLayout] for the function currently being compiled.
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fn on_new_block(&mut self)

A hook that triggers when first emitting a new block. It is guaranteed to be called before any instructions are emitted.

Auto Trait Implementations§

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impl Freeze for MInst

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impl RefUnwindSafe for MInst

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impl Send for MInst

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impl Sync for MInst

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impl Unpin for MInst

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impl UnwindSafe for MInst

Blanket Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> CloneToUninit for T
where T: Clone,

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unsafe fn clone_to_uninit(&self, dst: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dst. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T> ToOwned for T
where T: Clone,

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type Owned = T

The resulting type after obtaining ownership.
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fn to_owned(&self) -> T

Creates owned data from borrowed data, usually by cloning. Read more
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fn clone_into(&self, target: &mut T)

Uses borrowed data to replace owned data, usually by cloning. Read more
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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.