Struct cranelift_codegen::isa::x64::encoding::vex::VexInstruction

pub struct VexInstruction { /* private fields */ }

Constructs a VEX-encoded instruction using a builder pattern. This approach makes it visually easier to transform something the manual’s syntax, VEX.128.66.0F 73 /7 ib to code: VexInstruction::new().length(...).prefix(...).map(...).w(true).opcode(0x1F).reg(...).rm(...).

Implementations

impl VexInstruction

pub fn new() -> Self

Construct a default VEX instruction.

pub fn length(self, length: VexVectorLength) -> Self

Set the length of the instruction.

pub fn prefix(self, prefix: LegacyPrefixes) -> Self

Set the legacy prefix byte of the instruction: None | 66 | F2 | F3. VEX instructions pack these into the prefix, not as separate bytes.

pub fn map(self, map: OpcodeMap) -> Self

Set the opcode map byte of the instruction: None | 0F | 0F38 | 0F3A. VEX instructions pack these into the prefix, not as separate bytes.

pub fn w(self, w: bool) -> Self

Set the W bit, denoted by .W1 or .W0 in the instruction string. Typically used to indicate an instruction using 64 bits of an operand (e.g. 64 bit lanes). EVEX packs this bit in the EVEX prefix; previous encodings used the REX prefix.

pub fn opcode(self, opcode: u8) -> Self

Set the instruction opcode byte.

pub fn reg(self, reg: impl Into<Register>) -> Self

Set the register to use for the reg bits; many instructions use this as the write operand.

pub fn opcode_ext(self, n: u8) -> Self

Some instructions use the ModRM.reg field as an opcode extension. This is usually denoted by a /n field in the manual.

pub fn rm(self, reg: impl Into<Register>) -> Self

Set the register to use for the rm bits; many instructions use this as the “read from register/memory” operand. Currently this does not support memory addressing (TODO).Setting this affects both the ModRM byte (rm section) and the VEX prefix (the extension bits for register encodings > 8).

pub fn vvvv(self, reg: impl Into<Register>) -> Self

Set the vvvv register; some instructions allow using this as a second, non-destructive source register in 3-operand instructions (e.g. 2 read, 1 write).

pub fn imm_reg(self, reg: impl Into<Register>) -> Self

Set the imm byte when used for a register. The reg bits are stored in imm8[7:4] with the lower bits unused. Overrides a previously set Self::imm field.

pub fn imm(self, imm: u8) -> Self

Set the imm byte. Overrides a previously set Self::imm_reg field.

pub fn encode<CS: ByteSink + ?Sized>(&self, sink: &mut CS)

Emit the VEX-encoded instruction to the code sink:

Trait Implementations

impl Default for VexInstruction

fn default() -> Self

Returns the “default value” for a type.