Enum cranelift_codegen::binemit::Reloc
source · pub enum Reloc {
Show 22 variants
Abs4,
Abs8,
X86PCRel4,
X86CallPCRel4,
X86CallPLTRel4,
X86GOTPCRel4,
X86SecRel,
Arm32Call,
Arm64Call,
S390xPCRel32Dbl,
S390xPLTRel32Dbl,
ElfX86_64TlsGd,
MachOX86_64Tlv,
MachOAarch64TlsAdrPage21,
MachOAarch64TlsAdrPageOff12,
Aarch64TlsGdAdrPage21,
Aarch64TlsGdAddLo12Nc,
Aarch64AdrGotPage21,
Aarch64Ld64GotLo12Nc,
RiscvCall,
S390xTlsGd64,
S390xTlsGdCall,
}
Expand description
Relocation kinds for every ISA
Variants§
Abs4
absolute 4-byte
Abs8
absolute 8-byte
X86PCRel4
x86 PC-relative 4-byte
X86CallPCRel4
x86 call to PC-relative 4-byte
X86CallPLTRel4
x86 call to PLT-relative 4-byte
X86GOTPCRel4
x86 GOT PC-relative 4-byte
X86SecRel
The 32-bit offset of the target from the beginning of its section.
Equivalent to IMAGE_REL_AMD64_SECREL
.
See: PE Format
Arm32Call
Arm32 call target
Arm64Call
Arm64 call target. Encoded as bottom 26 bits of instruction. This value is sign-extended, multiplied by 4, and added to the PC of the call instruction to form the destination address.
S390xPCRel32Dbl
s390x PC-relative 4-byte offset
S390xPLTRel32Dbl
s390x PC-relative 4-byte offset to PLT
ElfX86_64TlsGd
Elf x86_64 32 bit signed PC relative offset to two GOT entries for GD symbol.
MachOX86_64Tlv
Mach-O x86_64 32 bit signed PC relative offset to a __thread_vars
entry.
MachOAarch64TlsAdrPage21
Mach-O Aarch64 TLS PC-relative distance to the page of the TLVP slot.
MachOAarch64TlsAdrPageOff12
Mach-O Aarch64 TLS Offset within page of TLVP slot.
Aarch64TlsGdAdrPage21
Aarch64 TLS GD
Set an ADRP immediate field to the top 21 bits of the final address. Checks for overflow.
This is equivalent to R_AARCH64_TLSGD_ADR_PAGE21
in the aaelf64
Aarch64TlsGdAddLo12Nc
Aarch64 TLS GD
Set the add immediate field to the low 12 bits of the final address. Does not check for overflow.
This is equivalent to R_AARCH64_TLSGD_ADD_LO12_NC
in the aaelf64
Aarch64AdrGotPage21
AArch64 GOT Page
Set the immediate value of an ADRP to bits 32:12 of X; check that –232 <= X < 232
This is equivalent to R_AARCH64_ADR_GOT_PAGE
(311) in the aaelf64
Aarch64Ld64GotLo12Nc
AArch64 GOT Low bits
Set the LD/ST immediate field to bits 11:3 of X. No overflow check; check that X&7 = 0
This is equivalent to R_AARCH64_LD64_GOT_LO12_NC
(312) in the aaelf64
RiscvCall
procedure call. call symbol expands to the following assembly and relocation: auipc ra, 0 jalr ra, ra, 0
S390xTlsGd64
s390x TLS GD64 - 64-bit offset of tls_index for GD symbol in GOT
S390xTlsGdCall
s390x TLS GDCall - marker to enable optimization of TLS calls
Trait Implementations§
source§impl PartialEq<Reloc> for Reloc
impl PartialEq<Reloc> for Reloc
impl Copy for Reloc
impl Eq for Reloc
impl StructuralEq for Reloc
impl StructuralPartialEq for Reloc
Auto Trait Implementations§
impl RefUnwindSafe for Reloc
impl Send for Reloc
impl Sync for Reloc
impl Unpin for Reloc
impl UnwindSafe for Reloc
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<Q, K> Equivalent<K> for Qwhere
Q: Eq + ?Sized,
K: Borrow<Q> + ?Sized,
impl<Q, K> Equivalent<K> for Qwhere Q: Eq + ?Sized, K: Borrow<Q> + ?Sized,
source§fn equivalent(&self, key: &K) -> bool
fn equivalent(&self, key: &K) -> bool
key
and return true
if they are equal.