Enum cranelift_codegen::isa::x64::Inst

pub enum Inst {
    Nop {
        len: u8,
    },
    AluRmiR {
        size: OperandSize,
        op: AluRmiROpcode,
        src1: Gpr,
        src2: GprMemImm,
        dst: WritableGpr,
    },
    AluRM {
        size: OperandSize,
        op: AluRmiROpcode,
        src1_dst: SyntheticAmode,
        src2: Gpr,
    },
    AluRmRVex {
        size: OperandSize,
        op: AluRmROpcode,
        src1: Gpr,
        src2: Gpr,
        dst: WritableGpr,
    },
    AluConstOp {
        op: AluRmiROpcode,
        size: OperandSize,
        dst: WritableGpr,
    },
    UnaryRmR {
        size: OperandSize,
        op: UnaryRmROpcode,
        src: GprMem,
        dst: WritableGpr,
    },
    Not {
        size: OperandSize,
        src: Gpr,
        dst: WritableGpr,
    },
    Neg {
        size: OperandSize,
        src: Gpr,
        dst: WritableGpr,
    },
    Div {
        size: OperandSize,
        sign: DivSignedness,
        trap: TrapCode,
        divisor: GprMem,
        dividend_lo: Gpr,
        dividend_hi: Gpr,
        dst_quotient: WritableGpr,
        dst_remainder: WritableGpr,
    },
    Div8 {
        sign: DivSignedness,
        trap: TrapCode,
        divisor: GprMem,
        dividend: Gpr,
        dst: WritableGpr,
    },
    MulHi {
        size: OperandSize,
        signed: bool,
        src1: Gpr,
        src2: GprMem,
        dst_lo: WritableGpr,
        dst_hi: WritableGpr,
    },
    CheckedSRemSeq {
        size: OperandSize,
        dividend_lo: Gpr,
        dividend_hi: Gpr,
        divisor: Gpr,
        dst_quotient: WritableGpr,
        dst_remainder: WritableGpr,
    },
    CheckedSRemSeq8 {
        dividend: Gpr,
        divisor: Gpr,
        dst: WritableGpr,
    },
    SignExtendData {
        size: OperandSize,
        src: Gpr,
        dst: WritableGpr,
    },
    Imm {
        dst_size: OperandSize,
        simm64: u64,
        dst: WritableGpr,
    },
    MovRR {
        size: OperandSize,
        src: Gpr,
        dst: WritableGpr,
    },
    MovFromPReg {
        src: PReg,
        dst: WritableGpr,
    },
    MovToPReg {
        src: Gpr,
        dst: PReg,
    },
    MovzxRmR {
        ext_mode: ExtMode,
        src: GprMem,
        dst: WritableGpr,
    },
    Mov64MR {
        src: SyntheticAmode,
        dst: WritableGpr,
    },
    LoadEffectiveAddress {
        addr: SyntheticAmode,
        dst: WritableGpr,
        size: OperandSize,
    },
    MovsxRmR {
        ext_mode: ExtMode,
        src: GprMem,
        dst: WritableGpr,
    },
    MovImmM {
        size: OperandSize,
        simm64: u64,
        dst: SyntheticAmode,
    },
    MovRM {
        size: OperandSize,
        src: Gpr,
        dst: SyntheticAmode,
    },
    ShiftR {
        size: OperandSize,
        kind: ShiftKind,
        src: Gpr,
        num_bits: Imm8Gpr,
        dst: WritableGpr,
    },
    XmmRmiReg {
        opcode: SseOpcode,
        src1: Xmm,
        src2: XmmMemAlignedImm,
        dst: WritableXmm,
    },
    CmpRmiR {
        size: OperandSize,
        opcode: CmpOpcode,
        src: GprMemImm,
        dst: Gpr,
    },
    Setcc {
        cc: CC,
        dst: WritableGpr,
    },
    Bswap {
        size: OperandSize,
        src: Gpr,
        dst: WritableGpr,
    },
    Cmove {
        size: OperandSize,
        cc: CC,
        consequent: GprMem,
        alternative: Gpr,
        dst: WritableGpr,
    },
    XmmCmove {
        ty: Type,
        cc: CC,
        consequent: XmmMemAligned,
        alternative: Xmm,
        dst: WritableXmm,
    },
    Push64 {
        src: GprMemImm,
    },
    Pop64 {
        dst: WritableGpr,
    },
    StackProbeLoop {
        tmp: Writable<Reg>,
        frame_size: u32,
        guard_size: u32,
    },
    XmmRmR {
        op: SseOpcode,
        src1: Xmm,
        src2: XmmMemAligned,
        dst: WritableXmm,
    },
    XmmRmRUnaligned {
        op: SseOpcode,
        src1: Xmm,
        src2: XmmMem,
        dst: WritableXmm,
    },
    XmmRmRBlend {
        op: SseOpcode,
        src1: Xmm,
        src2: XmmMemAligned,
        mask: Xmm,
        dst: WritableXmm,
    },
    XmmRmiRVex {
        op: AvxOpcode,
        src1: Xmm,
        src2: XmmMemImm,
        dst: WritableXmm,
    },
    XmmRmRImmVex {
        op: AvxOpcode,
        src1: Xmm,
        src2: XmmMem,
        dst: WritableXmm,
        imm: u8,
    },
    XmmVexPinsr {
        op: AvxOpcode,
        src1: Xmm,
        src2: GprMem,
        dst: WritableXmm,
        imm: u8,
    },
    XmmRmRVex3 {
        op: AvxOpcode,
        src1: Xmm,
        src2: Xmm,
        src3: XmmMem,
        dst: WritableXmm,
    },
    XmmRmRBlendVex {
        op: AvxOpcode,
        src1: Xmm,
        src2: XmmMem,
        mask: Xmm,
        dst: WritableXmm,
    },
    XmmUnaryRmRVex {
        op: AvxOpcode,
        src: XmmMem,
        dst: WritableXmm,
    },
    XmmUnaryRmRImmVex {
        op: AvxOpcode,
        src: XmmMem,
        dst: WritableXmm,
        imm: u8,
    },
    XmmMovRMVex {
        op: AvxOpcode,
        src: Xmm,
        dst: SyntheticAmode,
    },
    XmmMovRMImmVex {
        op: AvxOpcode,
        src: Xmm,
        dst: SyntheticAmode,
        imm: u8,
    },
    XmmToGprImmVex {
        op: AvxOpcode,
        src: Xmm,
        dst: WritableGpr,
        imm: u8,
    },
    GprToXmmVex {
        op: AvxOpcode,
        src: GprMem,
        dst: WritableXmm,
        src_size: OperandSize,
    },
    XmmToGprVex {
        op: AvxOpcode,
        src: Xmm,
        dst: WritableGpr,
        dst_size: OperandSize,
    },
    XmmRmREvex {
        op: Avx512Opcode,
        src1: XmmMem,
        src2: Xmm,
        dst: WritableXmm,
    },
    XmmRmREvex3 {
        op: Avx512Opcode,
        src1: XmmMem,
        src2: Xmm,
        src3: Xmm,
        dst: WritableXmm,
    },
    XmmUnaryRmR {
        op: SseOpcode,
        src: XmmMemAligned,
        dst: WritableXmm,
    },
    XmmUnaryRmRUnaligned {
        op: SseOpcode,
        src: XmmMem,
        dst: WritableXmm,
    },
    XmmUnaryRmRImm {
        op: SseOpcode,
        src: XmmMemAligned,
        imm: u8,
        dst: WritableXmm,
    },
    XmmUnaryRmREvex {
        op: Avx512Opcode,
        src: XmmMem,
        dst: WritableXmm,
    },
    XmmMovRM {
        op: SseOpcode,
        src: Xmm,
        dst: SyntheticAmode,
    },
    XmmMovRMImm {
        op: SseOpcode,
        src: Xmm,
        dst: SyntheticAmode,
        imm: u8,
    },
    XmmToGpr {
        op: SseOpcode,
        src: Xmm,
        dst: WritableGpr,
        dst_size: OperandSize,
    },
    XmmToGprImm {
        op: SseOpcode,
        src: Xmm,
        dst: WritableGpr,
        imm: u8,
    },
    GprToXmm {
        op: SseOpcode,
        src: GprMem,
        dst: WritableXmm,
        src_size: OperandSize,
    },
    CvtUint64ToFloatSeq {
        dst_size: OperandSize,
        src: Gpr,
        dst: WritableXmm,
        tmp_gpr1: WritableGpr,
        tmp_gpr2: WritableGpr,
    },
    CvtFloatToSintSeq {
        dst_size: OperandSize,
        src_size: OperandSize,
        is_saturating: bool,
        src: Xmm,
        dst: WritableGpr,
        tmp_gpr: WritableGpr,
        tmp_xmm: WritableXmm,
    },
    CvtFloatToUintSeq {
        dst_size: OperandSize,
        src_size: OperandSize,
        is_saturating: bool,
        src: Xmm,
        dst: WritableGpr,
        tmp_gpr: WritableGpr,
        tmp_xmm: WritableXmm,
        tmp_xmm2: WritableXmm,
    },
    XmmMinMaxSeq {
        size: OperandSize,
        is_min: bool,
        lhs: Xmm,
        rhs: Xmm,
        dst: WritableXmm,
    },
    XmmCmpRmR {
        op: SseOpcode,
        src: XmmMemAligned,
        dst: Xmm,
    },
    XmmRmRImm {
        op: SseOpcode,
        src1: Reg,
        src2: RegMem,
        dst: Writable<Reg>,
        imm: u8,
        size: OperandSize,
    },
    CallKnown {
        dest: ExternalName,
        info: Box<CallInfo>,
    },
    CallUnknown {
        dest: RegMem,
        info: Box<CallInfo>,
    },
    Args {
        args: Vec<ArgPair>,
    },
    Ret {
        rets: Vec<RetPair>,
    },
    JmpKnown {
        dst: MachLabel,
    },
    JmpIf {
        cc: CC,
        taken: MachLabel,
    },
    JmpCond {
        cc: CC,
        taken: MachLabel,
        not_taken: MachLabel,
    },
    JmpTableSeq {
        idx: Reg,
        tmp1: Writable<Reg>,
        tmp2: Writable<Reg>,
        default_target: MachLabel,
        targets: Box<SmallVec<[MachLabel; 4]>>,
    },
    JmpUnknown {
        target: RegMem,
    },
    TrapIf {
        cc: CC,
        trap_code: TrapCode,
    },
    TrapIfAnd {
        cc1: CC,
        cc2: CC,
        trap_code: TrapCode,
    },
    TrapIfOr {
        cc1: CC,
        cc2: CC,
        trap_code: TrapCode,
    },
    Hlt,
    Ud2 {
        trap_code: TrapCode,
    },
    LoadExtName {
        dst: Writable<Reg>,
        name: Box<ExternalName>,
        offset: i64,
    },
    LockCmpxchg {
        ty: Type,
        replacement: Reg,
        expected: Reg,
        mem: SyntheticAmode,
        dst_old: Writable<Reg>,
    },
    AtomicRmwSeq {
        ty: Type,
        op: MachAtomicRmwOp,
        mem: SyntheticAmode,
        operand: Reg,
        temp: Writable<Reg>,
        dst_old: Writable<Reg>,
    },
    Fence {
        kind: FenceKind,
    },
    VirtualSPOffsetAdj {
        offset: i64,
    },
    XmmUninitializedValue {
        dst: WritableXmm,
    },
    ElfTlsGetAddr {
        symbol: ExternalName,
        dst: WritableGpr,
    },
    MachOTlsGetAddr {
        symbol: ExternalName,
        dst: WritableGpr,
    },
    CoffTlsGetAddr {
        symbol: ExternalName,
        dst: WritableGpr,
        tmp: WritableGpr,
    },
    Unwind {
        inst: UnwindInst,
    },
    DummyUse {
        reg: Reg,
    },
}

Internal type MInst: defined at src/isa/x64/inst.isle line 8.

Variants

Nop

Fields

len: u8

AluRmiR

Fields

size: OperandSize

op: AluRmiROpcode

src1: Gpr

src2: GprMemImm

dst: WritableGpr

AluRM

Fields

size: OperandSize

op: AluRmiROpcode

src1_dst: SyntheticAmode

src2: Gpr

AluRmRVex

Fields

size: OperandSize

op: AluRmROpcode

src1: Gpr

src2: Gpr

dst: WritableGpr

AluConstOp

Fields

op: AluRmiROpcode

size: OperandSize

dst: WritableGpr

UnaryRmR

Fields

size: OperandSize

op: UnaryRmROpcode

src: GprMem

dst: WritableGpr

Not

Fields

size: OperandSize

src: Gpr

dst: WritableGpr

Neg

Fields

size: OperandSize

src: Gpr

dst: WritableGpr

Div

Fields

size: OperandSize

sign: DivSignedness

trap: TrapCode

divisor: GprMem

dividend_lo: Gpr

dividend_hi: Gpr

dst_quotient: WritableGpr

dst_remainder: WritableGpr

Div8

Fields

sign: DivSignedness

trap: TrapCode

divisor: GprMem

dividend: Gpr

dst: WritableGpr

MulHi

Fields

size: OperandSize

signed: bool

src1: Gpr

src2: GprMem

dst_lo: WritableGpr

dst_hi: WritableGpr

CheckedSRemSeq

Fields

size: OperandSize

dividend_lo: Gpr

dividend_hi: Gpr

divisor: Gpr

dst_quotient: WritableGpr

dst_remainder: WritableGpr

CheckedSRemSeq8

Fields

dividend: Gpr

divisor: Gpr

dst: WritableGpr

SignExtendData

Fields

size: OperandSize

src: Gpr

dst: WritableGpr

Imm

Fields

dst_size: OperandSize

simm64: u64

dst: WritableGpr

MovRR

Fields

size: OperandSize

src: Gpr

dst: WritableGpr

MovFromPReg

Fields

src: PReg

dst: WritableGpr

MovToPReg

Fields

src: Gpr

dst: PReg

MovzxRmR

Fields

ext_mode: ExtMode

src: GprMem

dst: WritableGpr

Mov64MR

Fields

src: SyntheticAmode

dst: WritableGpr

LoadEffectiveAddress

Fields

addr: SyntheticAmode

dst: WritableGpr

size: OperandSize

MovsxRmR

Fields

ext_mode: ExtMode

src: GprMem

dst: WritableGpr

MovImmM

Fields

size: OperandSize

simm64: u64

dst: SyntheticAmode

MovRM

Fields

size: OperandSize

src: Gpr

dst: SyntheticAmode

ShiftR

Fields

size: OperandSize

kind: ShiftKind

src: Gpr

num_bits: Imm8Gpr

dst: WritableGpr

XmmRmiReg

Fields

opcode: SseOpcode

src1: Xmm

src2: XmmMemAlignedImm

dst: WritableXmm

CmpRmiR

Fields

size: OperandSize

opcode: CmpOpcode

src: GprMemImm

dst: Gpr

Setcc

Fields

cc: CC

dst: WritableGpr

Bswap

Fields

size: OperandSize

src: Gpr

dst: WritableGpr

Cmove

Fields

size: OperandSize

cc: CC

consequent: GprMem

alternative: Gpr

dst: WritableGpr

XmmCmove

Fields

ty: Type

cc: CC

consequent: XmmMemAligned

alternative: Xmm

dst: WritableXmm

Push64

Fields

src: GprMemImm

Pop64

Fields

dst: WritableGpr

StackProbeLoop

Fields

tmp: Writable<Reg>

frame_size: u32

guard_size: u32

XmmRmR

Fields

op: SseOpcode

src1: Xmm

src2: XmmMemAligned

dst: WritableXmm

XmmRmRUnaligned

Fields

op: SseOpcode

src1: Xmm

src2: XmmMem

dst: WritableXmm

XmmRmRBlend

Fields

op: SseOpcode

src1: Xmm

src2: XmmMemAligned

mask: Xmm

dst: WritableXmm

XmmRmiRVex

Fields

op: AvxOpcode

src1: Xmm

src2: XmmMemImm

dst: WritableXmm

XmmRmRImmVex

Fields

op: AvxOpcode

src1: Xmm

src2: XmmMem

dst: WritableXmm

imm: u8

XmmVexPinsr

Fields

op: AvxOpcode

src1: Xmm

src2: GprMem

dst: WritableXmm

imm: u8

XmmRmRVex3

Fields

op: AvxOpcode

src1: Xmm

src2: Xmm

src3: XmmMem

dst: WritableXmm

XmmRmRBlendVex

Fields

op: AvxOpcode

src1: Xmm

src2: XmmMem

mask: Xmm

dst: WritableXmm

XmmUnaryRmRVex

Fields

op: AvxOpcode

src: XmmMem

dst: WritableXmm

XmmUnaryRmRImmVex

Fields

op: AvxOpcode

src: XmmMem

dst: WritableXmm

imm: u8

XmmMovRMVex

Fields

op: AvxOpcode

src: Xmm

dst: SyntheticAmode

XmmMovRMImmVex

Fields

op: AvxOpcode

src: Xmm

dst: SyntheticAmode

imm: u8

XmmToGprImmVex

Fields

op: AvxOpcode

src: Xmm

dst: WritableGpr

imm: u8

GprToXmmVex

Fields

op: AvxOpcode

src: GprMem

dst: WritableXmm

src_size: OperandSize

XmmToGprVex

Fields

op: AvxOpcode

src: Xmm

dst: WritableGpr

dst_size: OperandSize

XmmRmREvex

Fields

op: Avx512Opcode

src1: XmmMem

src2: Xmm

dst: WritableXmm

XmmRmREvex3

Fields

op: Avx512Opcode

src1: XmmMem

src2: Xmm

src3: Xmm

dst: WritableXmm

XmmUnaryRmR

Fields

op: SseOpcode

src: XmmMemAligned

dst: WritableXmm

XmmUnaryRmRUnaligned

Fields

op: SseOpcode

src: XmmMem

dst: WritableXmm

XmmUnaryRmRImm

Fields

op: SseOpcode

src: XmmMemAligned

imm: u8

dst: WritableXmm

XmmUnaryRmREvex

Fields

op: Avx512Opcode

src: XmmMem

dst: WritableXmm

XmmMovRM

Fields

op: SseOpcode

src: Xmm

dst: SyntheticAmode

XmmMovRMImm

Fields

op: SseOpcode

src: Xmm

dst: SyntheticAmode

imm: u8

XmmToGpr

Fields

op: SseOpcode

src: Xmm

dst: WritableGpr

dst_size: OperandSize

XmmToGprImm

Fields

op: SseOpcode

src: Xmm

dst: WritableGpr

imm: u8

GprToXmm

Fields

op: SseOpcode

src: GprMem

dst: WritableXmm

src_size: OperandSize

CvtUint64ToFloatSeq

Fields

dst_size: OperandSize

src: Gpr

dst: WritableXmm

tmp_gpr1: WritableGpr

tmp_gpr2: WritableGpr

CvtFloatToSintSeq

Fields

dst_size: OperandSize

src_size: OperandSize

is_saturating: bool

src: Xmm

dst: WritableGpr

tmp_gpr: WritableGpr

tmp_xmm: WritableXmm

CvtFloatToUintSeq

Fields

dst_size: OperandSize

src_size: OperandSize

is_saturating: bool

src: Xmm

dst: WritableGpr

tmp_gpr: WritableGpr

tmp_xmm: WritableXmm

tmp_xmm2: WritableXmm

XmmMinMaxSeq

Fields

size: OperandSize

is_min: bool

lhs: Xmm

rhs: Xmm

dst: WritableXmm

XmmCmpRmR

Fields

op: SseOpcode

src: XmmMemAligned

dst: Xmm

XmmRmRImm

Fields

op: SseOpcode

src1: Reg

src2: RegMem

dst: Writable<Reg>

imm: u8

size: OperandSize

CallKnown

Fields

dest: ExternalName

info: Box<CallInfo>

CallUnknown

Fields

dest: RegMem

info: Box<CallInfo>

Args

Fields

args: Vec<ArgPair>

Ret

Fields

rets: Vec<RetPair>

JmpKnown

Fields

dst: MachLabel

JmpIf

Fields

cc: CC

taken: MachLabel

JmpCond

Fields

cc: CC

taken: MachLabel

not_taken: MachLabel

JmpTableSeq

Fields

idx: Reg

tmp1: Writable<Reg>

tmp2: Writable<Reg>

default_target: MachLabel

targets: Box<SmallVec<[MachLabel; 4]>>

JmpUnknown

Fields

target: RegMem

TrapIf

Fields

cc: CC

trap_code: TrapCode

TrapIfAnd

Fields

cc1: CC

cc2: CC

trap_code: TrapCode

TrapIfOr

Fields

cc1: CC

cc2: CC

trap_code: TrapCode

Hlt

Ud2

Fields

trap_code: TrapCode

LoadExtName

Fields

dst: Writable<Reg>

name: Box<ExternalName>

offset: i64

LockCmpxchg

Fields

ty: Type

replacement: Reg

expected: Reg

mem: SyntheticAmode

dst_old: Writable<Reg>

AtomicRmwSeq

Fields

ty: Type

op: MachAtomicRmwOp

mem: SyntheticAmode

operand: Reg

temp: Writable<Reg>

dst_old: Writable<Reg>

Fence

Fields

kind: FenceKind

VirtualSPOffsetAdj

Fields

offset: i64

XmmUninitializedValue

Fields

dst: WritableXmm

ElfTlsGetAddr

Fields

symbol: ExternalName

dst: WritableGpr

MachOTlsGetAddr

Fields

symbol: ExternalName

dst: WritableGpr

CoffTlsGetAddr

Fields

symbol: ExternalName

dst: WritableGpr

tmp: WritableGpr

Unwind

Fields

inst: UnwindInst

DummyUse

Fields

reg: Reg

Trait Implementations

impl Clone for MInst

fn clone(&self) -> MInst

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Inst

fn fmt(&self, fmt: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl MachInst for Inst

type ABIMachineSpec = X64ABIMachineSpec

The ABI machine spec for this MachInst.

fn get_operands<F: Fn(VReg) -> VReg>( &self, collector: &mut OperandCollector<'_, F> )

Return the registers referenced by this machine instruction along with the modes of reference (use, def, modify).

fn is_move(&self) -> Option<(Writable<Reg>, Reg)>

If this is a simple move, return the (source, destination) tuple of registers.

fn is_included_in_clobbers(&self) -> bool

Should this instruction be included in the clobber-set?

fn is_trap(&self) -> bool

Is this an unconditional trap?

fn is_args(&self) -> bool

Is this an “args” pseudoinst?

fn is_term(&self) -> MachTerminator

Is this a terminator (branch or ret)? If so, return its type (ret/uncond/cond) and target if applicable.

fn gen_move(dst_reg: Writable<Reg>, src_reg: Reg, ty: Type) -> Inst

Generate a move.

fn gen_nop(preferred_size: usize) -> Inst

Generate a NOP. The preferred_size parameter allows the caller to request a NOP of that size, or as close to it as possible. The machine backend may return a NOP whose binary encoding is smaller than the preferred size, but must not return a NOP that is larger. However, the instruction must have a nonzero size if preferred_size is nonzero.

fn rc_for_type( ty: Type ) -> CodegenResult<(&'static [RegClass], &'static [Type])>

Determine register class(es) to store the given Cranelift type, and the Cranelift type actually stored in the underlying register(s). May return an error if the type isn’t supported by this backend.

fn canonical_type_for_rc(rc: RegClass) -> Type

Get an appropriate type that can fully hold a value in a given register class. This may not be the only type that maps to that class, but when used with gen_move() or the ABI trait’s load/spill constructors, it should produce instruction(s) that move the entire register contents.

fn gen_jump(label: MachLabel) -> Inst

Generate a jump to another target. Used during lowering of control flow.

fn gen_dummy_use(reg: Reg) -> Self

Generate a dummy instruction that will keep a value alive but has no other purpose.

fn worst_case_size() -> CodeOffset

What is the worst-case instruction size emitted by this instruction type?

fn ref_type_regclass(_: &Flags) -> RegClass

What is the register class used for reference types (GC-observable pointers)? Can be dependent on compilation flags.

fn is_safepoint(&self) -> bool

Is this a safepoint?

type LabelUse = LabelUse

A label-use kind: a type that describes the types of label references that can occur in an instruction.

const TRAP_OPCODE: &'static [u8] = _

Byte representation of a trap opcode which is inserted by MachBuffer during its defer_trap method.

fn align_basic_block(offset: CodeOffset) -> CodeOffset

Align a basic block offset (from start of function). By default, no alignment occurs.

fn gen_block_start( _is_indirect_branch_target: bool, _is_forward_edge_cfi_enabled: bool ) -> Option<Self>

Generate an instruction that must appear at the beginning of a basic block, if any. Note that the return value must not be subject to register allocation.

impl MachInstEmit for Inst

type State = EmitState

Persistent state carried across emit invocations.

type Info = EmitInfo

Constant information used in emit invocations.

fn emit( &self, allocs: &[Allocation], sink: &mut MachBuffer<Inst>, info: &Self::Info, state: &mut Self::State )

Emit the instruction.

fn pretty_print_inst( &self, allocs: &[Allocation], _: &mut Self::State ) -> String

Pretty-print the instruction.