cache-padded 1.3.0

Prevent false sharing by padding and aligning to the length of a cache line
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83

# cache-padded (deprecated)

[![Build](https://github.com/smol-rs/cache-padded/workflows/Build%20and%20test/badge.svg)](
https://github.com/smol-rs/cache-padded/actions)
[![License](https://img.shields.io/badge/license-Apache--2.0_OR_MIT-blue.svg)](
https://github.com/smol-rs/cache-padded)
[![Cargo](https://img.shields.io/crates/v/cache-padded.svg)](
https://crates.io/crates/cache-padded)
[![Documentation](https://docs.rs/cache-padded/badge.svg)](
https://docs.rs/cache-padded)

**This crate is now deprecated in favor of [crossbeam-utils::CachePadded](https://docs.rs/crossbeam-utils/latest/crossbeam_utils/struct.CachePadded.html).**

Prevent false sharing by padding and aligning to the length of a cache line.

In concurrent programming, sometimes it is desirable to make sure commonly accessed shared data
is not all placed into the same cache line. Updating an atomic value invalides the whole cache
line it belongs to, which makes the next access to the same cache line slower for other CPU
cores. Use `CachePadded` to ensure updating one piece of data doesn't invalidate other cached
data.

## Size and alignment

Cache lines are assumed to be N bytes long, depending on the architecture:

* On x86-64, aarch64, and powerpc64, N = 128.
* On arm, mips, mips64, and riscv64, N = 32.
* On s390x, N = 256.
* On all others, N = 64.

Note that N is just a reasonable guess and is not guaranteed to match the actual cache line
length of the machine the program is running on.

The size of `CachePadded<T>` is the smallest multiple of N bytes large enough to accommodate
a value of type `T`.

The alignment of `CachePadded<T>` is the maximum of N bytes and the alignment of `T`.

## Examples

Alignment and padding:

```rust
use cache_padded::CachePadded;

let array = [CachePadded::new(1i8), CachePadded::new(2i8)];
let addr1 = &*array[0] as *const i8 as usize;
let addr2 = &*array[1] as *const i8 as usize;

assert!(addr2 - addr1 >= 64);
assert_eq!(addr1 % 64, 0);
assert_eq!(addr2 % 64, 0);
```

When building a concurrent queue with a head and a tail index, it is wise to place indices in
different cache lines so that concurrent threads pushing and popping elements don't invalidate
each other's cache lines:

```rust
use cache_padded::CachePadded;
use std::sync::atomic::AtomicUsize;

struct Queue<T> {
    head: CachePadded<AtomicUsize>,
    tail: CachePadded<AtomicUsize>,
    buffer: *mut T,
}
```

## License

Licensed under either of

 * Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)
 * MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)

at your option.

#### Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted
for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
dual licensed as above, without any additional terms or conditions.