pub struct ThermalPowerInfo { /* private fields */ }Expand description
Query information about thermal and power management features of the CPU (LEAF=0x06).
§Platforms
🟡 AMD ✅ Intel
Implementations§
source§impl ThermalPowerInfo
impl ThermalPowerInfo
sourcepub fn dts_irq_threshold(&self) -> u8
pub fn dts_irq_threshold(&self) -> u8
Number of Interrupt Thresholds in Digital Thermal Sensor
§Platforms
❌ AMD (undefined/reserved) ✅ Intel
sourcepub fn has_turbo_boost(&self) -> bool
pub fn has_turbo_boost(&self) -> bool
Intel Turbo Boost Technology Available (see description of IA32_MISC_ENABLE[38]).
§Platforms
❌ AMD (reserved) ✅ Intel
sourcepub fn has_ecmd(&self) -> bool
pub fn has_ecmd(&self) -> bool
ECMD. Clock modulation duty cycle extension is supported if set.
§Platforms
❌ AMD (reserved) ✅ Intel
sourcepub fn has_hwp(&self) -> bool
pub fn has_hwp(&self) -> bool
HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
§Platforms
❌ AMD (reserved) ✅ Intel
sourcepub fn has_hwp_notification(&self) -> bool
pub fn has_hwp_notification(&self) -> bool
sourcepub fn has_hwp_activity_window(&self) -> bool
pub fn has_hwp_activity_window(&self) -> bool
HWP Activity Window. IA32_HWP_REQUEST[bits 41:32] is supported if set.
§Platforms
❌ AMD (reserved) ✅ Intel
sourcepub fn has_hwp_energy_performance_preference(&self) -> bool
pub fn has_hwp_energy_performance_preference(&self) -> bool
HWP Energy Performance Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set.
§Platforms
❌ AMD (reserved) ✅ Intel
sourcepub fn has_hwp_package_level_request(&self) -> bool
pub fn has_hwp_package_level_request(&self) -> bool
HWP Package Level Request. IA32_HWP_REQUEST_PKG MSR is supported if set.
§Platforms
❌ AMD (reserved) ✅ Intel
sourcepub fn has_hdc(&self) -> bool
pub fn has_hdc(&self) -> bool
HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are supported if set.
§Platforms
❌ AMD (reserved) ✅ Intel
sourcepub fn has_turbo_boost3(&self) -> bool
pub fn has_turbo_boost3(&self) -> bool
sourcepub fn has_hwp_capabilities(&self) -> bool
pub fn has_hwp_capabilities(&self) -> bool
HWP Capabilities. Highest Performance change is supported if set.
§Platforms
❌ AMD (reserved) ✅ Intel
sourcepub fn has_hwp_peci_override(&self) -> bool
pub fn has_hwp_peci_override(&self) -> bool
sourcepub fn has_flexible_hwp(&self) -> bool
pub fn has_flexible_hwp(&self) -> bool
sourcepub fn has_hwp_fast_access_mode(&self) -> bool
pub fn has_hwp_fast_access_mode(&self) -> bool
Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.
§Platforms
❌ AMD (reserved) ✅ Intel
sourcepub fn has_ignore_idle_processor_hwp_request(&self) -> bool
pub fn has_ignore_idle_processor_hwp_request(&self) -> bool
Ignoring Idle Logical Processor HWP request is supported if set.
§Platforms
❌ AMD (reserved) ✅ Intel
sourcepub fn has_hw_coord_feedback(&self) -> bool
pub fn has_hw_coord_feedback(&self) -> bool
Hardware Coordination Feedback Capability
Presence of IA32_MPERF and IA32_APERF.
The capability to provide a measure of delivered processor performance (since last reset of the counters), as a percentage of expected processor performance at frequency specified in CPUID Brand String Bits 02 - 01
§Platforms
✅ AMD ✅ Intel
sourcepub fn has_energy_bias_pref(&self) -> bool
pub fn has_energy_bias_pref(&self) -> bool
The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H)
§Platforms
❌ AMD (reserved) ✅ Intel