riscv 0.12.1

Low level access to RISC-V processors
Documentation 
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[dependencies.critical-section]
version = "1.2.0"

[dependencies.embedded-hal]
version = "1.0.0"

[dependencies.paste]
version = "1.0.15"

[dependencies.riscv-macros]
optional = true
version = "0.1.0"

[dependencies.riscv-pac]
version = "0.2.0"

[features]
critical-section-single-hart = ["critical-section/restore-state-bool"]
default = ["riscv-macros"]
s-mode = []

[lib]
name = "riscv"
path = "src/lib.rs"

[package]
authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
autobenches = false
autobins = false
autoexamples = false
autotests = false
build = "build.rs"
categories = ["embedded", "hardware-support", "no-std"]
description = "Low level access to RISC-V processors"
documentation = "https://docs.rs/riscv"
edition = "2021"
keywords = ["riscv", "register", "peripheral"]
license = "ISC"
name = "riscv"
readme = "README.md"
repository = "https://github.com/rust-embedded/riscv"
rust-version = "1.61"
version = "0.12.1"

[package.metadata.docs.rs]
all-features = true
default-target = "riscv64imac-unknown-none-elf"
targets = ["riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf", "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf"]