[package]
name = "rust-hdl-ok-core"
version = "0.10.2"
edition = "2021"
license = "MIT"
description = "Generic support code for OpalKelly based FPGA modules that use the FrontPanel HDL interface"
homepage = "https://rusthdl.org"
repository = "https://github.com/SmithsDigitalForge/rust-hdl"
keywords = ["fpga", "verilog", "hardware"]
authors = ["Samit Basu <samit.basu@smiths.com>"]
[dependencies]
rust-hdl = {version= "^0.38.0", path="../rust-hdl"}
rust-hdl-fpga-support = {version= "^0.8.0", path="../rust-hdl-fpga-support"}
rust-hdl-ok-frontpanel-sys = {version= "0.8.0", path="../rust-hdl-ok-frontpanel-sys"}
regex = "1.5.4"
rand = "0.8.5"