Struct hipDeviceProp_tR0600

#[repr(C)]
pub struct hipDeviceProp_tR0600 {

    pub name: [c_char; 256],
    pub uuid: hipUUID,
    pub luid: [c_char; 8],
    pub luidDeviceNodeMask: c_uint,
    pub totalGlobalMem: usize,
    pub sharedMemPerBlock: usize,
    pub regsPerBlock: c_int,
    pub warpSize: c_int,
    pub memPitch: usize,
    pub maxThreadsPerBlock: c_int,
    pub maxThreadsDim: [c_int; 3],
    pub maxGridSize: [c_int; 3],
    pub clockRate: c_int,
    pub totalConstMem: usize,
    pub major: c_int,
    pub minor: c_int,
    pub textureAlignment: usize,
    pub texturePitchAlignment: usize,
    pub deviceOverlap: c_int,
    pub multiProcessorCount: c_int,
    pub kernelExecTimeoutEnabled: c_int,
    pub integrated: c_int,
    pub canMapHostMemory: c_int,
    pub computeMode: c_int,
    pub maxTexture1D: c_int,
    pub maxTexture1DMipmap: c_int,
    pub maxTexture1DLinear: c_int,
    pub maxTexture2D: [c_int; 2],
    pub maxTexture2DMipmap: [c_int; 2],
    pub maxTexture2DLinear: [c_int; 3],
    pub maxTexture2DGather: [c_int; 2],
    pub maxTexture3D: [c_int; 3],
    pub maxTexture3DAlt: [c_int; 3],
    pub maxTextureCubemap: c_int,
    pub maxTexture1DLayered: [c_int; 2],
    pub maxTexture2DLayered: [c_int; 3],
    pub maxTextureCubemapLayered: [c_int; 2],
    pub maxSurface1D: c_int,
    pub maxSurface2D: [c_int; 2],
    pub maxSurface3D: [c_int; 3],
    pub maxSurface1DLayered: [c_int; 2],
    pub maxSurface2DLayered: [c_int; 3],
    pub maxSurfaceCubemap: c_int,
    pub maxSurfaceCubemapLayered: [c_int; 2],
    pub surfaceAlignment: usize,
    pub concurrentKernels: c_int,
    pub ECCEnabled: c_int,
    pub pciBusID: c_int,
    pub pciDeviceID: c_int,
    pub pciDomainID: c_int,
    pub tccDriver: c_int,
    pub asyncEngineCount: c_int,
    pub unifiedAddressing: c_int,
    pub memoryClockRate: c_int,
    pub memoryBusWidth: c_int,
    pub l2CacheSize: c_int,
    pub persistingL2CacheMaxSize: c_int,
    pub maxThreadsPerMultiProcessor: c_int,
    pub streamPrioritiesSupported: c_int,
    pub globalL1CacheSupported: c_int,
    pub localL1CacheSupported: c_int,
    pub sharedMemPerMultiprocessor: usize,
    pub regsPerMultiprocessor: c_int,
    pub managedMemory: c_int,
    pub isMultiGpuBoard: c_int,
    pub multiGpuBoardGroupID: c_int,
    pub hostNativeAtomicSupported: c_int,
    pub singleToDoublePrecisionPerfRatio: c_int,
    pub pageableMemoryAccess: c_int,
    pub concurrentManagedAccess: c_int,
    pub computePreemptionSupported: c_int,
    pub canUseHostPointerForRegisteredMem: c_int,
    pub cooperativeLaunch: c_int,
    pub cooperativeMultiDeviceLaunch: c_int,
    pub sharedMemPerBlockOptin: usize,
    pub pageableMemoryAccessUsesHostPageTables: c_int,
    pub directManagedMemAccessFromHost: c_int,
    pub maxBlocksPerMultiProcessor: c_int,
    pub accessPolicyMaxWindowSize: c_int,
    pub reservedSharedMemPerBlock: usize,
    pub hostRegisterSupported: c_int,
    pub sparseHipArraySupported: c_int,
    pub hostRegisterReadOnlySupported: c_int,
    pub timelineSemaphoreInteropSupported: c_int,
    pub memoryPoolsSupported: c_int,
    pub gpuDirectRDMASupported: c_int,
    pub gpuDirectRDMAFlushWritesOptions: c_uint,
    pub gpuDirectRDMAWritesOrdering: c_int,
    pub memoryPoolSupportedHandleTypes: c_uint,
    pub deferredMappingHipArraySupported: c_int,
    pub ipcEventSupported: c_int,
    pub clusterLaunch: c_int,
    pub unifiedFunctionPointers: c_int,
    pub reserved: [c_int; 63],
    pub hipReserved: [c_int; 32],
    pub gcnArchName: [c_char; 256],
    pub maxSharedMemoryPerMultiProcessor: usize,
    pub clockInstructionRate: c_int,
    pub arch: hipDeviceArch_t,
    pub hdpMemFlushCntl: *mut c_uint,
    pub hdpRegFlushCntl: *mut c_uint,
    pub cooperativeMultiDeviceUnmatchedFunc: c_int,
    pub cooperativeMultiDeviceUnmatchedGridDim: c_int,
    pub cooperativeMultiDeviceUnmatchedBlockDim: c_int,
    pub cooperativeMultiDeviceUnmatchedSharedMem: c_int,
    pub isLargeBar: c_int,
    pub asicRevision: c_int,
}

hipDeviceProp

Fields

name: [c_char; 256]

< Device name.

uuid: hipUUID

< UUID of a device

luid: [c_char; 8]

< 8-byte unique identifier. Only valid on windows

luidDeviceNodeMask: c_uint

< LUID node mask

totalGlobalMem: usize

< Size of global memory region (in bytes).

sharedMemPerBlock: usize

< Size of shared memory per block (in bytes).

regsPerBlock: c_int

< Registers per block.

warpSize: c_int

< Warp size.

memPitch: usize

< Maximum pitch in bytes allowed by memory copies < pitched memory

maxThreadsPerBlock: c_int

< Max work items per work group or workgroup max size.

maxThreadsDim: [c_int; 3]

< Max number of threads in each dimension (XYZ) of a block.

maxGridSize: [c_int; 3]

< Max grid dimensions (XYZ).

clockRate: c_int

< Max clock frequency of the multiProcessors in khz.

totalConstMem: usize

< Size of shared constant memory region on the device < (in bytes).

major: c_int

< Major compute capability. On HCC, this is an approximation and features may < differ from CUDA CC. See the arch feature flags for portable ways to query < feature caps.

minor: c_int

< Minor compute capability. On HCC, this is an approximation and features may < differ from CUDA CC. See the arch feature flags for portable ways to query < feature caps.

textureAlignment: usize

< Alignment requirement for textures

texturePitchAlignment: usize

< Pitch alignment requirement for texture references bound to

deviceOverlap: c_int

< Deprecated. Use asyncEngineCount instead

multiProcessorCount: c_int

< Number of multi-processors (compute units).

kernelExecTimeoutEnabled: c_int

< Run time limit for kernels executed on the device

integrated: c_int

< APU vs dGPU

canMapHostMemory: c_int

< Check whether HIP can map host memory

computeMode: c_int

< Compute mode.

maxTexture1D: c_int

< Maximum number of elements in 1D images

maxTexture1DMipmap: c_int

< Maximum 1D mipmap texture size

maxTexture1DLinear: c_int

< Maximum size for 1D textures bound to linear memory

maxTexture2D: [c_int; 2]

< Maximum dimensions (width, height) of 2D images, in image elements

maxTexture2DMipmap: [c_int; 2]

< Maximum number of elements in 2D array mipmap of images

maxTexture2DLinear: [c_int; 3]

< Maximum 2D tex dimensions if tex are bound to pitched memory

maxTexture2DGather: [c_int; 2]

< Maximum 2D tex dimensions if gather has to be performed

maxTexture3D: [c_int; 3]

< Maximum dimensions (width, height, depth) of 3D images, in image < elements

maxTexture3DAlt: [c_int; 3]

< Maximum alternate 3D texture dims

maxTextureCubemap: c_int

< Maximum cubemap texture dims

maxTexture1DLayered: [c_int; 2]

< Maximum number of elements in 1D array images

maxTexture2DLayered: [c_int; 3]

< Maximum number of elements in 2D array images

maxTextureCubemapLayered: [c_int; 2]

< Maximum cubemaps layered texture dims

maxSurface1D: c_int

< Maximum 1D surface size

maxSurface2D: [c_int; 2]

< Maximum 2D surface size

maxSurface3D: [c_int; 3]

< Maximum 3D surface size

maxSurface1DLayered: [c_int; 2]

< Maximum 1D layered surface size

maxSurface2DLayered: [c_int; 3]

< Maximum 2D layared surface size

maxSurfaceCubemap: c_int

< Maximum cubemap surface size

maxSurfaceCubemapLayered: [c_int; 2]

< Maximum cubemap layered surface size

surfaceAlignment: usize

< Alignment requirement for surface

concurrentKernels: c_int

< Device can possibly execute multiple kernels concurrently.

ECCEnabled: c_int

< Device has ECC support enabled

pciBusID: c_int

< PCI Bus ID.

pciDeviceID: c_int

< PCI Device ID.

pciDomainID: c_int

< PCI Domain ID

tccDriver: c_int

< 1:If device is Tesla device using TCC driver, else 0

asyncEngineCount: c_int

< Number of async engines

unifiedAddressing: c_int

< Does device and host share unified address space

memoryClockRate: c_int

< Max global memory clock frequency in khz.

memoryBusWidth: c_int

< Global memory bus width in bits.

l2CacheSize: c_int

< L2 cache size.

persistingL2CacheMaxSize: c_int

< Device’s max L2 persisting lines in bytes

maxThreadsPerMultiProcessor: c_int

< Maximum resident threads per multi-processor.

streamPrioritiesSupported: c_int

< Device supports stream priority

globalL1CacheSupported: c_int

< Indicates globals are cached in L1

localL1CacheSupported: c_int

< Locals are cahced in L1

sharedMemPerMultiprocessor: usize

< Amount of shared memory available per multiprocessor.

regsPerMultiprocessor: c_int

< registers available per multiprocessor

managedMemory: c_int

< Device supports allocating managed memory on this system

isMultiGpuBoard: c_int

< 1 if device is on a multi-GPU board, 0 if not.

multiGpuBoardGroupID: c_int

< Unique identifier for a group of devices on same multiboard GPU

hostNativeAtomicSupported: c_int

< Link between host and device supports native atomics

singleToDoublePrecisionPerfRatio: c_int

< Deprecated. CUDA only.

pageableMemoryAccess: c_int

< Device supports coherently accessing pageable memory < without calling hipHostRegister on it

concurrentManagedAccess: c_int

< Device can coherently access managed memory concurrently with < the CPU

computePreemptionSupported: c_int

< Is compute preemption supported on the device

canUseHostPointerForRegisteredMem: c_int

< Device can access host registered memory with same < address as the host

cooperativeLaunch: c_int

< HIP device supports cooperative launch

cooperativeMultiDeviceLaunch: c_int

< HIP device supports cooperative launch on multiple < devices

sharedMemPerBlockOptin: usize

< Per device m ax shared mem per block usable by special opt in

pageableMemoryAccessUsesHostPageTables: c_int

< Device accesses pageable memory via the host’s < page tables

directManagedMemAccessFromHost: c_int

< Host can directly access managed memory on the device < without migration

maxBlocksPerMultiProcessor: c_int

< Max number of blocks on CU

accessPolicyMaxWindowSize: c_int

< Max value of access policy window

reservedSharedMemPerBlock: usize

< Shared memory reserved by driver per block

hostRegisterSupported: c_int

< Device supports hipHostRegister

sparseHipArraySupported: c_int

< Indicates if device supports sparse hip arrays

hostRegisterReadOnlySupported: c_int

< Device supports using the hipHostRegisterReadOnly flag < with hipHostRegistger

timelineSemaphoreInteropSupported: c_int

< Indicates external timeline semaphore support

memoryPoolsSupported: c_int

< Indicates if device supports hipMallocAsync and hipMemPool APIs

gpuDirectRDMASupported: c_int

< Indicates device support of RDMA APIs

gpuDirectRDMAFlushWritesOptions: c_uint

< Bitmask to be interpreted according to < hipFlushGPUDirectRDMAWritesOptions

gpuDirectRDMAWritesOrdering: c_int

< value of hipGPUDirectRDMAWritesOrdering

memoryPoolSupportedHandleTypes: c_uint

< Bitmask of handle types support with mempool based IPC

deferredMappingHipArraySupported: c_int

< Device supports deferred mapping HIP arrays and HIP < mipmapped arrays

ipcEventSupported: c_int

< Device supports IPC events

clusterLaunch: c_int

< Device supports cluster launch

unifiedFunctionPointers: c_int

< Indicates device supports unified function pointers

reserved: [c_int; 63]

< CUDA Reserved.

hipReserved: [c_int; 32]

< Reserved for adding new entries for HIP/CUDA.

gcnArchName: [c_char; 256]

< AMD GCN Arch Name. HIP Only.

maxSharedMemoryPerMultiProcessor: usize

< Maximum Shared Memory Per CU. HIP Only.

clockInstructionRate: c_int

< Frequency in khz of the timer used by the device-side “clock*” < instructions. New for HIP.

arch: hipDeviceArch_t

< Architectural feature flags. New for HIP.

hdpMemFlushCntl: *mut c_uint

< Addres of HDP_MEM_COHERENCY_FLUSH_CNTL register

hdpRegFlushCntl: *mut c_uint

< Addres of HDP_REG_COHERENCY_FLUSH_CNTL register

cooperativeMultiDeviceUnmatchedFunc: c_int

< HIP device supports cooperative launch on < multiple

cooperativeMultiDeviceUnmatchedGridDim: c_int

< HIP device supports cooperative launch on < multiple

cooperativeMultiDeviceUnmatchedBlockDim: c_int

< HIP device supports cooperative launch on < multiple

cooperativeMultiDeviceUnmatchedSharedMem: c_int

< HIP device supports cooperative launch on < multiple

isLargeBar: c_int

< 1: if it is a large PCI bar device, else 0

asicRevision: c_int

< Revision of the GPU in this device

Trait Implementations

impl Clone for hipDeviceProp_tR0600

fn clone(&self) -> hipDeviceProp_tR0600

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for hipDeviceProp_tR0600

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Copy for hipDeviceProp_tR0600