Struct embassy_stm32::fmc::Fmc

pub struct Fmc<'d, T: Instance> { /* private fields */ }

FMC driver

Implementations

impl<'d, T> Fmc<'d, T>

where T: Instance,

pub fn new_raw(_instance: impl Peripheral<P = T> + 'd) -> Self

Create a raw FMC instance.

Note: This is currently used to provide access to some basic FMC functions for manual configuration for memory types that stm32-fmc does not support.

pub fn enable(&mut self)

Enable the FMC peripheral and reset it.

pub fn memory_controller_enable(&mut self)

Enable the memory controller on applicable chips.

pub fn source_clock_hz(&self) -> u32

Get the kernel clock currently in use for this FMC instance.

impl<'d, T: Instance> Fmc<'d, T>

pub fn sdram_a12bits_d16bits_4banks_bank1<CHIP: SdramChip>( _instance: impl Peripheral<P = T> + 'd, a0: impl Peripheral<P = impl A0Pin<T>> + 'd, a1: impl Peripheral<P = impl A1Pin<T>> + 'd, a2: impl Peripheral<P = impl A2Pin<T>> + 'd, a3: impl Peripheral<P = impl A3Pin<T>> + 'd, a4: impl Peripheral<P = impl A4Pin<T>> + 'd, a5: impl Peripheral<P = impl A5Pin<T>> + 'd, a6: impl Peripheral<P = impl A6Pin<T>> + 'd, a7: impl Peripheral<P = impl A7Pin<T>> + 'd, a8: impl Peripheral<P = impl A8Pin<T>> + 'd, a9: impl Peripheral<P = impl A9Pin<T>> + 'd, a10: impl Peripheral<P = impl A10Pin<T>> + 'd, a11: impl Peripheral<P = impl A11Pin<T>> + 'd, ba0: impl Peripheral<P = impl BA0Pin<T>> + 'd, ba1: impl Peripheral<P = impl BA1Pin<T>> + 'd, d0: impl Peripheral<P = impl D0Pin<T>> + 'd, d1: impl Peripheral<P = impl D1Pin<T>> + 'd, d2: impl Peripheral<P = impl D2Pin<T>> + 'd, d3: impl Peripheral<P = impl D3Pin<T>> + 'd, d4: impl Peripheral<P = impl D4Pin<T>> + 'd, d5: impl Peripheral<P = impl D5Pin<T>> + 'd, d6: impl Peripheral<P = impl D6Pin<T>> + 'd, d7: impl Peripheral<P = impl D7Pin<T>> + 'd, d8: impl Peripheral<P = impl D8Pin<T>> + 'd, d9: impl Peripheral<P = impl D9Pin<T>> + 'd, d10: impl Peripheral<P = impl D10Pin<T>> + 'd, d11: impl Peripheral<P = impl D11Pin<T>> + 'd, d12: impl Peripheral<P = impl D12Pin<T>> + 'd, d13: impl Peripheral<P = impl D13Pin<T>> + 'd, d14: impl Peripheral<P = impl D14Pin<T>> + 'd, d15: impl Peripheral<P = impl D15Pin<T>> + 'd, nbl0: impl Peripheral<P = impl NBL0Pin<T>> + 'd, nbl1: impl Peripheral<P = impl NBL1Pin<T>> + 'd, sdcke: impl Peripheral<P = impl SDCKE0Pin<T>> + 'd, sdclk: impl Peripheral<P = impl SDCLKPin<T>> + 'd, sdncas: impl Peripheral<P = impl SDNCASPin<T>> + 'd, sdne: impl Peripheral<P = impl SDNE0Pin<T>> + 'd, sdnras: impl Peripheral<P = impl SDNRASPin<T>> + 'd, sdnwe: impl Peripheral<P = impl SDNWEPin<T>> + 'd, chip: CHIP ) -> Sdram<Fmc<'d, T>, CHIP>

Create a new FMC instance.

pub fn sdram_a12bits_d32bits_4banks_bank1<CHIP: SdramChip>( _instance: impl Peripheral<P = T> + 'd, a0: impl Peripheral<P = impl A0Pin<T>> + 'd, a1: impl Peripheral<P = impl A1Pin<T>> + 'd, a2: impl Peripheral<P = impl A2Pin<T>> + 'd, a3: impl Peripheral<P = impl A3Pin<T>> + 'd, a4: impl Peripheral<P = impl A4Pin<T>> + 'd, a5: impl Peripheral<P = impl A5Pin<T>> + 'd, a6: impl Peripheral<P = impl A6Pin<T>> + 'd, a7: impl Peripheral<P = impl A7Pin<T>> + 'd, a8: impl Peripheral<P = impl A8Pin<T>> + 'd, a9: impl Peripheral<P = impl A9Pin<T>> + 'd, a10: impl Peripheral<P = impl A10Pin<T>> + 'd, a11: impl Peripheral<P = impl A11Pin<T>> + 'd, ba0: impl Peripheral<P = impl BA0Pin<T>> + 'd, ba1: impl Peripheral<P = impl BA1Pin<T>> + 'd, d0: impl Peripheral<P = impl D0Pin<T>> + 'd, d1: impl Peripheral<P = impl D1Pin<T>> + 'd, d2: impl Peripheral<P = impl D2Pin<T>> + 'd, d3: impl Peripheral<P = impl D3Pin<T>> + 'd, d4: impl Peripheral<P = impl D4Pin<T>> + 'd, d5: impl Peripheral<P = impl D5Pin<T>> + 'd, d6: impl Peripheral<P = impl D6Pin<T>> + 'd, d7: impl Peripheral<P = impl D7Pin<T>> + 'd, d8: impl Peripheral<P = impl D8Pin<T>> + 'd, d9: impl Peripheral<P = impl D9Pin<T>> + 'd, d10: impl Peripheral<P = impl D10Pin<T>> + 'd, d11: impl Peripheral<P = impl D11Pin<T>> + 'd, d12: impl Peripheral<P = impl D12Pin<T>> + 'd, d13: impl Peripheral<P = impl D13Pin<T>> + 'd, d14: impl Peripheral<P = impl D14Pin<T>> + 'd, d15: impl Peripheral<P = impl D15Pin<T>> + 'd, d16: impl Peripheral<P = impl D16Pin<T>> + 'd, d17: impl Peripheral<P = impl D17Pin<T>> + 'd, d18: impl Peripheral<P = impl D18Pin<T>> + 'd, d19: impl Peripheral<P = impl D19Pin<T>> + 'd, d20: impl Peripheral<P = impl D20Pin<T>> + 'd, d21: impl Peripheral<P = impl D21Pin<T>> + 'd, d22: impl Peripheral<P = impl D22Pin<T>> + 'd, d23: impl Peripheral<P = impl D23Pin<T>> + 'd, d24: impl Peripheral<P = impl D24Pin<T>> + 'd, d25: impl Peripheral<P = impl D25Pin<T>> + 'd, d26: impl Peripheral<P = impl D26Pin<T>> + 'd, d27: impl Peripheral<P = impl D27Pin<T>> + 'd, d28: impl Peripheral<P = impl D28Pin<T>> + 'd, d29: impl Peripheral<P = impl D29Pin<T>> + 'd, d30: impl Peripheral<P = impl D30Pin<T>> + 'd, d31: impl Peripheral<P = impl D31Pin<T>> + 'd, nbl0: impl Peripheral<P = impl NBL0Pin<T>> + 'd, nbl1: impl Peripheral<P = impl NBL1Pin<T>> + 'd, nbl2: impl Peripheral<P = impl NBL2Pin<T>> + 'd, nbl3: impl Peripheral<P = impl NBL3Pin<T>> + 'd, sdcke: impl Peripheral<P = impl SDCKE0Pin<T>> + 'd, sdclk: impl Peripheral<P = impl SDCLKPin<T>> + 'd, sdncas: impl Peripheral<P = impl SDNCASPin<T>> + 'd, sdne: impl Peripheral<P = impl SDNE0Pin<T>> + 'd, sdnras: impl Peripheral<P = impl SDNRASPin<T>> + 'd, sdnwe: impl Peripheral<P = impl SDNWEPin<T>> + 'd, chip: CHIP ) -> Sdram<Fmc<'d, T>, CHIP>

Create a new FMC instance.

pub fn sdram_a12bits_d16bits_4banks_bank2<CHIP: SdramChip>( _instance: impl Peripheral<P = T> + 'd, a0: impl Peripheral<P = impl A0Pin<T>> + 'd, a1: impl Peripheral<P = impl A1Pin<T>> + 'd, a2: impl Peripheral<P = impl A2Pin<T>> + 'd, a3: impl Peripheral<P = impl A3Pin<T>> + 'd, a4: impl Peripheral<P = impl A4Pin<T>> + 'd, a5: impl Peripheral<P = impl A5Pin<T>> + 'd, a6: impl Peripheral<P = impl A6Pin<T>> + 'd, a7: impl Peripheral<P = impl A7Pin<T>> + 'd, a8: impl Peripheral<P = impl A8Pin<T>> + 'd, a9: impl Peripheral<P = impl A9Pin<T>> + 'd, a10: impl Peripheral<P = impl A10Pin<T>> + 'd, a11: impl Peripheral<P = impl A11Pin<T>> + 'd, ba0: impl Peripheral<P = impl BA0Pin<T>> + 'd, ba1: impl Peripheral<P = impl BA1Pin<T>> + 'd, d0: impl Peripheral<P = impl D0Pin<T>> + 'd, d1: impl Peripheral<P = impl D1Pin<T>> + 'd, d2: impl Peripheral<P = impl D2Pin<T>> + 'd, d3: impl Peripheral<P = impl D3Pin<T>> + 'd, d4: impl Peripheral<P = impl D4Pin<T>> + 'd, d5: impl Peripheral<P = impl D5Pin<T>> + 'd, d6: impl Peripheral<P = impl D6Pin<T>> + 'd, d7: impl Peripheral<P = impl D7Pin<T>> + 'd, d8: impl Peripheral<P = impl D8Pin<T>> + 'd, d9: impl Peripheral<P = impl D9Pin<T>> + 'd, d10: impl Peripheral<P = impl D10Pin<T>> + 'd, d11: impl Peripheral<P = impl D11Pin<T>> + 'd, d12: impl Peripheral<P = impl D12Pin<T>> + 'd, d13: impl Peripheral<P = impl D13Pin<T>> + 'd, d14: impl Peripheral<P = impl D14Pin<T>> + 'd, d15: impl Peripheral<P = impl D15Pin<T>> + 'd, nbl0: impl Peripheral<P = impl NBL0Pin<T>> + 'd, nbl1: impl Peripheral<P = impl NBL1Pin<T>> + 'd, sdcke: impl Peripheral<P = impl SDCKE1Pin<T>> + 'd, sdclk: impl Peripheral<P = impl SDCLKPin<T>> + 'd, sdncas: impl Peripheral<P = impl SDNCASPin<T>> + 'd, sdne: impl Peripheral<P = impl SDNE1Pin<T>> + 'd, sdnras: impl Peripheral<P = impl SDNRASPin<T>> + 'd, sdnwe: impl Peripheral<P = impl SDNWEPin<T>> + 'd, chip: CHIP ) -> Sdram<Fmc<'d, T>, CHIP>

Create a new FMC instance.

pub fn sdram_a12bits_d32bits_4banks_bank2<CHIP: SdramChip>( _instance: impl Peripheral<P = T> + 'd, a0: impl Peripheral<P = impl A0Pin<T>> + 'd, a1: impl Peripheral<P = impl A1Pin<T>> + 'd, a2: impl Peripheral<P = impl A2Pin<T>> + 'd, a3: impl Peripheral<P = impl A3Pin<T>> + 'd, a4: impl Peripheral<P = impl A4Pin<T>> + 'd, a5: impl Peripheral<P = impl A5Pin<T>> + 'd, a6: impl Peripheral<P = impl A6Pin<T>> + 'd, a7: impl Peripheral<P = impl A7Pin<T>> + 'd, a8: impl Peripheral<P = impl A8Pin<T>> + 'd, a9: impl Peripheral<P = impl A9Pin<T>> + 'd, a10: impl Peripheral<P = impl A10Pin<T>> + 'd, a11: impl Peripheral<P = impl A11Pin<T>> + 'd, ba0: impl Peripheral<P = impl BA0Pin<T>> + 'd, ba1: impl Peripheral<P = impl BA1Pin<T>> + 'd, d0: impl Peripheral<P = impl D0Pin<T>> + 'd, d1: impl Peripheral<P = impl D1Pin<T>> + 'd, d2: impl Peripheral<P = impl D2Pin<T>> + 'd, d3: impl Peripheral<P = impl D3Pin<T>> + 'd, d4: impl Peripheral<P = impl D4Pin<T>> + 'd, d5: impl Peripheral<P = impl D5Pin<T>> + 'd, d6: impl Peripheral<P = impl D6Pin<T>> + 'd, d7: impl Peripheral<P = impl D7Pin<T>> + 'd, d8: impl Peripheral<P = impl D8Pin<T>> + 'd, d9: impl Peripheral<P = impl D9Pin<T>> + 'd, d10: impl Peripheral<P = impl D10Pin<T>> + 'd, d11: impl Peripheral<P = impl D11Pin<T>> + 'd, d12: impl Peripheral<P = impl D12Pin<T>> + 'd, d13: impl Peripheral<P = impl D13Pin<T>> + 'd, d14: impl Peripheral<P = impl D14Pin<T>> + 'd, d15: impl Peripheral<P = impl D15Pin<T>> + 'd, d16: impl Peripheral<P = impl D16Pin<T>> + 'd, d17: impl Peripheral<P = impl D17Pin<T>> + 'd, d18: impl Peripheral<P = impl D18Pin<T>> + 'd, d19: impl Peripheral<P = impl D19Pin<T>> + 'd, d20: impl Peripheral<P = impl D20Pin<T>> + 'd, d21: impl Peripheral<P = impl D21Pin<T>> + 'd, d22: impl Peripheral<P = impl D22Pin<T>> + 'd, d23: impl Peripheral<P = impl D23Pin<T>> + 'd, d24: impl Peripheral<P = impl D24Pin<T>> + 'd, d25: impl Peripheral<P = impl D25Pin<T>> + 'd, d26: impl Peripheral<P = impl D26Pin<T>> + 'd, d27: impl Peripheral<P = impl D27Pin<T>> + 'd, d28: impl Peripheral<P = impl D28Pin<T>> + 'd, d29: impl Peripheral<P = impl D29Pin<T>> + 'd, d30: impl Peripheral<P = impl D30Pin<T>> + 'd, d31: impl Peripheral<P = impl D31Pin<T>> + 'd, nbl0: impl Peripheral<P = impl NBL0Pin<T>> + 'd, nbl1: impl Peripheral<P = impl NBL1Pin<T>> + 'd, nbl2: impl Peripheral<P = impl NBL2Pin<T>> + 'd, nbl3: impl Peripheral<P = impl NBL3Pin<T>> + 'd, sdcke: impl Peripheral<P = impl SDCKE1Pin<T>> + 'd, sdclk: impl Peripheral<P = impl SDCLKPin<T>> + 'd, sdncas: impl Peripheral<P = impl SDNCASPin<T>> + 'd, sdne: impl Peripheral<P = impl SDNE1Pin<T>> + 'd, sdnras: impl Peripheral<P = impl SDNRASPin<T>> + 'd, sdnwe: impl Peripheral<P = impl SDNWEPin<T>> + 'd, chip: CHIP ) -> Sdram<Fmc<'d, T>, CHIP>

Create a new FMC instance.

Trait Implementations

impl<'d, T> FmcPeripheral for Fmc<'d, T>

where T: Instance,

const REGISTERS: *const () = _

Pointer to the register block

fn enable(&mut self)

Enables the FMC on its peripheral bus

fn memory_controller_enable(&mut self)

Enables the FMC memory controller (not always required)

fn source_clock_hz(&self) -> u32

The frequency of the clock used as a source for the fmc_clk.

impl<'d, T> Send for Fmc<'d, T>

where T: Instance,