Module esp32c2_hal::efuse
source · Expand description
Reading of eFuses (ESP32-C2)
Overview
The efuse
module provides functionality for reading eFuse data
from the ESP32-C2
chip, allowing access to various chip-specific
information such as :
- MAC address
- core count
- CPU frequency
- chip type
and more. It is useful for retrieving chip-specific configuration and identification data during runtime.
The Efuse
struct represents the eFuse peripheral and is responsible for
reading various eFuse fields and values.
Example
Read chip’s MAC address from the eFuse storage.
let mac_address = Efuse::get_mac_address();
writeln!(
serial_tx,
"MAC: {:#X}:{:#X}:{:#X}:{:#X}:{:#X}:{:#X}",
mac_address[0],
mac_address[1],
mac_address[2],
mac_address[3],
mac_address[4],
mac_address[5]
);
Structs
- The bit field for get access to efuse data
Constants
[]
ADC1 calibration voltage at atten0[]
ADC1 calibration voltage at atten3[]
ADC1 init code at atten0[]
ADC1 init code at atten3[]
Store the bit[86:96]
of ADC calibration data[]
Major version of BLOCK2[]
Minor version of BLOCK2 {0: “No calib”; 1: “With calib”}[ENABLE_CUSTOM_MAC]
True if MAC_CUSTOM is burned[]
BLOCK2 digital dbias when hvt[]
BLOCK2 DIG_LDO_ACT_DBIAS26[]
BLOCK2 DIG_LDO_ACT_STEPD10[]
BLOCK2 DIG_LDO_DBG0_DBIAS2[]
BLOCK2 DIG_LDO_DBG0_DBIAS26[]
Disables check of blk version major[]
Disables check of wafer version major[]
This bit set means disable direct_boot mode[]
The bit be set to disable icache in download mode[]
The bit be set to disable manual encryption[]
Set this bit to disable download mode (boot_mode[3:0]
= 0; 1; 2; 4; 5; 6; 7)[]
Set this bit to disable pad jtag[]
Set this bit to enable secure UART download mode[]
Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value[]
Set this bit to force ROM code to send a resume command during SPI boot[BLOCK_KEY0]
BLOCK_BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryption[]
128bit FE key[]
256bit FE key[]
128bit SB key[MAC_FACTORY]
MAC address[]
OCode[]
EFUSE_PKG_VERSION[]
Disable reading from BlOCK3[]
Read protection for EFUSE_BLK3. KEY0[]
Read protection for EFUSE_BLK3. KEY0 higher 128-bit key[]
Read protection for EFUSE_BLK3. KEY0 lower 128-bit key[]
BLOCK2 DIG_LDO_ACT_DBIAS13[]
BLOCK2 DIG_LDO_ACT_DBIAS31[]
BLOCK2 DIG_LDO_SLP_DBIAS13[]
BLOCK2 DIG_LDO_SLP_DBIAS29[]
BLOCK2 DIG_LDO_SLP_DBIAS31[]
The bit be set to enable secure boot[]
Secure version for anti-rollback[]
Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: “Disable”; 1: “Enable”; 3: “Disable”; 7: “Enable”}[]
Temperature calibration data[]
Set the default UARTboot message output mode {0: “Enable”; 1: “Enable when GPIO8 is low at reset”; 2: “Enable when GPIO8 is high at reset”; 3: “Disable”}[]
User data block[MAC_CUSTOM CUSTOM_MAC]
Custom MAC address[]
WAFER_VERSION_MAJOR[]
WAFER_VERSION_MINOR[]
RTC watchdog timeout threshold; in unit of slow clock cycle {0: “40000”; 1: “80000”; 2: “160000”; 3: “320000”}[]
Disable programming of individual eFuses[]
wr_dis of ADC1_CAL_VOL_ATTEN0[]
wr_dis of ADC1_CAL_VOL_ATTEN3[]
wr_dis of ADC1_INIT_CODE_ATTEN0[]
wr_dis of ADC1_INIT_CODE_ATTEN3[]
wr_dis of ADC_CALIBRATION_3[]
wr_dis of BLK_VERSION_MAJOR[]
wr_dis of BLK_VERSION_MINOR[WR_DIS.KEY0]
wr_dis of BLOCK_KEY0[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]
wr_dis of CUSTOM_MAC[WR_DIS.ENABLE_CUSTOM_MAC]
wr_dis of CUSTOM_MAC_USED[]
wr_dis of DIG_DBIAS_HVT[]
wr_dis of DIG_LDO_ACT_DBIAS26[]
wr_dis of DIG_LDO_ACT_STEPD10[]
wr_dis of DIG_LDO_SLP_DBIAS2[]
wr_dis of DIG_LDO_SLP_DBIAS26[]
wr_dis of DISABLE_BLK_VERSION_MAJOR[]
wr_dis of DISABLE_WAFER_VERSION_MAJOR[]
wr_dis of DIS_DIRECT_BOOT[]
wr_dis of DIS_DOWNLOAD_ICACHE[]
wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT[]
wr_dis of DIS_DOWNLOAD_MODE[]
wr_dis of DIS_PAD_JTAG[]
wr_dis of ENABLE_SECURITY_DOWNLOAD[]
wr_dis of FLASH_TPUW[]
wr_dis of FORCE_SEND_RESUME[WR_DIS.MAC_FACTORY]
wr_dis of MAC[]
wr_dis of OCODE[]
wr_dis of PKG_VERSION[]
wr_dis of RD_DIS[]
wr_dis of RTC_LDO_ACT_DBIAS13[]
wr_dis of RTC_LDO_ACT_DBIAS31[]
wr_dis of RTC_LDO_SLP_DBIAS13[]
wr_dis of RTC_LDO_SLP_DBIAS29[]
wr_dis of RTC_LDO_SLP_DBIAS31[]
wr_dis of SECURE_BOOT_EN[]
wr_dis of SECURE_VERSION[]
wr_dis of SPI_BOOT_CRYPT_CNT[]
wr_dis of TEMP_CALIB[]
wr_dis of UART_PRINT_CONTROL[]
wr_dis of WAFER_VERSION_MAJOR[]
wr_dis of WAFER_VERSION_MINOR[]
wr_dis of WDT_DELAY_SEL[]
wr_dis of XTS_KEY_LENGTH_256[]
Flash encryption key length {0: “128 bits key”; 1: “256 bits key”}