Enum esp32c3_hal::peripherals::Interrupt
#[repr(u16)]pub enum Interrupt {
Show 62 variants
WIFI_MAC = 0,
WIFI_MAC_NMI = 1,
WIFI_PWR = 2,
WIFI_BB = 3,
BT_MAC = 4,
BT_BB = 5,
BT_BB_NMI = 6,
RWBT = 7,
RWBLE = 8,
RWBT_NMI = 9,
RWBLE_NMI = 10,
I2C_MASTER = 11,
SLC0 = 12,
SLC1 = 13,
APB_CTRL = 14,
UHCI0 = 15,
GPIO = 16,
GPIO_NMI = 17,
SPI1 = 18,
SPI2 = 19,
I2S0 = 20,
UART0 = 21,
UART1 = 22,
LEDC = 23,
EFUSE = 24,
TWAI0 = 25,
USB_DEVICE = 26,
RTC_CORE = 27,
RMT = 28,
I2C_EXT0 = 29,
TIMER1 = 30,
TIMER2 = 31,
TG0_T0_LEVEL = 32,
TG0_WDT_LEVEL = 33,
TG1_T0_LEVEL = 34,
TG1_WDT_LEVEL = 35,
CACHE_IA = 36,
SYSTIMER_TARGET0 = 37,
SYSTIMER_TARGET1 = 38,
SYSTIMER_TARGET2 = 39,
SPI_MEM_REJECT_CACHE = 40,
ICACHE_PRELOAD0 = 41,
ICACHE_SYNC0 = 42,
APB_ADC = 43,
DMA_CH0 = 44,
DMA_CH1 = 45,
DMA_CH2 = 46,
RSA = 47,
AES = 48,
SHA = 49,
FROM_CPU_INTR0 = 50,
FROM_CPU_INTR1 = 51,
FROM_CPU_INTR2 = 52,
FROM_CPU_INTR3 = 53,
ASSIST_DEBUG = 54,
DMA_APBPERI_PMS = 55,
CORE0_IRAM0_PMS = 56,
CORE0_DRAM0_PMS = 57,
CORE0_PIF_PMS = 58,
CORE0_PIF_PMS_SIZE = 59,
BAK_PMS_VIOLATE = 60,
CACHE_CORE0_ACS = 61,
}
Expand description
Enumeration of all the interrupts.
Variants§
WIFI_MAC = 0
0 - WIFI_MAC
WIFI_MAC_NMI = 1
1 - WIFI_MAC_NMI
WIFI_PWR = 2
2 - WIFI_PWR
WIFI_BB = 3
3 - WIFI_BB
BT_MAC = 4
4 - BT_MAC
BT_BB = 5
5 - BT_BB
BT_BB_NMI = 6
6 - BT_BB_NMI
RWBT = 7
7 - RWBT
RWBLE = 8
8 - RWBLE
RWBT_NMI = 9
9 - RWBT_NMI
RWBLE_NMI = 10
10 - RWBLE_NMI
I2C_MASTER = 11
11 - I2C_MASTER
SLC0 = 12
12 - SLC0
SLC1 = 13
13 - SLC1
APB_CTRL = 14
14 - APB_CTRL
UHCI0 = 15
15 - UHCI0
GPIO = 16
16 - GPIO
GPIO_NMI = 17
17 - GPIO_NMI
SPI1 = 18
18 - SPI1
SPI2 = 19
19 - SPI2
I2S0 = 20
20 - I2S0
UART0 = 21
21 - UART0
UART1 = 22
22 - UART1
LEDC = 23
23 - LEDC
EFUSE = 24
24 - EFUSE
TWAI0 = 25
25 - TWAI0
USB_DEVICE = 26
26 - USB_DEVICE
RTC_CORE = 27
27 - RTC_CORE
RMT = 28
28 - RMT
I2C_EXT0 = 29
29 - I2C_EXT0
TIMER1 = 30
30 - TIMER1
TIMER2 = 31
31 - TIMER2
TG0_T0_LEVEL = 32
32 - TG0_T0_LEVEL
TG0_WDT_LEVEL = 33
33 - TG0_WDT_LEVEL
TG1_T0_LEVEL = 34
34 - TG1_T0_LEVEL
TG1_WDT_LEVEL = 35
35 - TG1_WDT_LEVEL
CACHE_IA = 36
36 - CACHE_IA
SYSTIMER_TARGET0 = 37
37 - SYSTIMER_TARGET0
SYSTIMER_TARGET1 = 38
38 - SYSTIMER_TARGET1
SYSTIMER_TARGET2 = 39
39 - SYSTIMER_TARGET2
SPI_MEM_REJECT_CACHE = 40
40 - SPI_MEM_REJECT_CACHE
ICACHE_PRELOAD0 = 41
41 - ICACHE_PRELOAD0
ICACHE_SYNC0 = 42
42 - ICACHE_SYNC0
APB_ADC = 43
43 - APB_ADC
DMA_CH0 = 44
44 - DMA_CH0
DMA_CH1 = 45
45 - DMA_CH1
DMA_CH2 = 46
46 - DMA_CH2
RSA = 47
47 - RSA
AES = 48
48 - AES
SHA = 49
49 - SHA
FROM_CPU_INTR0 = 50
50 - FROM_CPU_INTR0
FROM_CPU_INTR1 = 51
51 - FROM_CPU_INTR1
FROM_CPU_INTR2 = 52
52 - FROM_CPU_INTR2
FROM_CPU_INTR3 = 53
53 - FROM_CPU_INTR3
ASSIST_DEBUG = 54
54 - ASSIST_DEBUG
DMA_APBPERI_PMS = 55
55 - DMA_APBPERI_PMS
CORE0_IRAM0_PMS = 56
56 - CORE0_IRAM0_PMS
CORE0_DRAM0_PMS = 57
57 - CORE0_DRAM0_PMS
CORE0_PIF_PMS = 58
58 - CORE0_PIF_PMS
CORE0_PIF_PMS_SIZE = 59
59 - CORE0_PIF_PMS_SIZE
BAK_PMS_VIOLATE = 60
60 - BAK_PMS_VIOLATE
CACHE_CORE0_ACS = 61
61 - CACHE_CORE0_ACS