Struct iced_x86::DecoderOptions
source · pub struct DecoderOptions;
Expand description
Decoder options
Implementations§
source§impl DecoderOptions
impl DecoderOptions
sourcepub const NO_INVALID_CHECK: u32 = 1u32
pub const NO_INVALID_CHECK: u32 = 1u32
Disable some checks for invalid encodings of instructions, eg. most instructions can’t use a LOCK
prefix so if one is found, they’re decoded as Code::INVALID
unless this option is enabled.
sourcepub const AMD: u32 = 2u32
pub const AMD: u32 = 2u32
AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS
, UD0
has no modr/m byte, decode LOCK MOV CR
. The AMD decoder can still decode Intel instructions.
sourcepub const FORCE_RESERVED_NOP: u32 = 4u32
pub const FORCE_RESERVED_NOP: u32 = 4u32
Decode opcodes 0F0D
and 0F18-0F1F
as reserved-nop instructions (eg. Code::Reservednop_rm32_r32_0F1D
)
sourcepub const CMPXCHG486A: u32 = 32u32
pub const CMPXCHG486A: u32 = 32u32
Decode 0FA6
/0FA7
as CMPXCHG
sourcepub const LOADALL286: u32 = 256u32
pub const LOADALL286: u32 = 256u32
Decode 286 STOREALL
/LOADALL
(0F04
and 0F05
)
sourcepub const LOADALL386: u32 = 512u32
pub const LOADALL386: u32 = 512u32
Decode 386 LOADALL
sourcepub const NO_WBNOINVD: u32 = 16_384u32
pub const NO_WBNOINVD: u32 = 16_384u32
Don’t decode WBNOINVD
, decode WBINVD
instead
sourcepub const NO_MPFX_0FBC: u32 = 65_536u32
pub const NO_MPFX_0FBC: u32 = 65_536u32
Don’t decode TZCNT
, decode BSF
instead
sourcepub const NO_MPFX_0FBD: u32 = 131_072u32
pub const NO_MPFX_0FBD: u32 = 131_072u32
Don’t decode LZCNT
, decode BSR
instead
sourcepub const NO_LAHF_SAHF_64: u32 = 262_144u32
pub const NO_LAHF_SAHF_64: u32 = 262_144u32
Don’t decode LAHF
and SAHF
in 64-bit mode
sourcepub const CYRIX_SMINT_0F7E: u32 = 2_097_152u32
pub const CYRIX_SMINT_0F7E: u32 = 2_097_152u32
Decode Cyrix SMINT 0F7E
(Cyrix 6x86 or earlier)