Module moore_svlog::lexer [−][src]
Expand description
A lexical analyzer for SystemVerilog files, based on IEEE 1800-2009, section 5.
Structs
A lexical analyzer for SystemVerilog files.
Enums
A delimiter token such as parentheses or brackets.
Abstract literals such as strings.
Operator symbols.
Expression precedence. Note that a few kinds of expression are right-associative rather than the default left-associative.
The unit of a time literal.
A primary token emitted by the lexer.