Module moore_svlog::mir [−][src]
Expand description
The medium-level intermediate representation for SystemVerilog.
Represents a fully typed SystemVerilog design with all implicit operations converted into explicit nodes.
Modules
Lowering to MIR.
Structs
An assignment of an Rvalue to an Lvalue.
An lvalue expression.
An rvalue expression.
Enums
The binary bitwise operators.
The integer binary arithmetic operators.
The integer comparison operators.
The integer unary arithmetic operators.
The different forms an lvalue expression may take.
The different forms an rvalue expression may take.
The shift operators.
The string comparison operators.
The unary bitwise operators.
Traits
A node that accepts Visitors.
A visitor.
A node that walks a Visitor over itself.