Enum Opcode

Source

#[repr(u8)]pub enum Opcode {
Show 140 variants    trap = 0,
    fallthrough = 17,
    jump_indirect = 19,
    load_imm = 4,
    load_u8 = 60,
    load_i8 = 74,
    load_u16 = 76,
    load_i16 = 66,
    load_i32 = 10,
    load_u32 = 102,
    load_u64 = 95,
    store_u8 = 71,
    store_u16 = 69,
    store_u32 = 22,
    store_u64 = 96,
    load_imm_and_jump = 6,
    branch_eq_imm = 7,
    branch_not_eq_imm = 15,
    branch_less_unsigned_imm = 44,
    branch_less_signed_imm = 32,
    branch_greater_or_equal_unsigned_imm = 52,
    branch_greater_or_equal_signed_imm = 45,
    branch_less_or_equal_signed_imm = 46,
    branch_less_or_equal_unsigned_imm = 59,
    branch_greater_signed_imm = 53,
    branch_greater_unsigned_imm = 50,
    store_imm_indirect_u8 = 26,
    store_imm_indirect_u16 = 54,
    store_imm_indirect_u32 = 13,
    store_imm_indirect_u64 = 93,
    store_indirect_u8 = 16,
    store_indirect_u16 = 29,
    store_indirect_u32 = 3,
    store_indirect_u64 = 90,
    load_indirect_u8 = 11,
    load_indirect_i8 = 21,
    load_indirect_u16 = 37,
    load_indirect_i16 = 33,
    load_indirect_i32 = 1,
    load_indirect_u32 = 99,
    load_indirect_u64 = 91,
    add_imm_32 = 2,
    add_imm_64 = 104,
    and_imm = 18,
    xor_imm = 31,
    or_imm = 49,
    mul_imm_32 = 35,
    mul_imm_64 = 121,
    set_less_than_unsigned_imm = 27,
    set_less_than_signed_imm = 56,
    shift_logical_left_imm_32 = 9,
    shift_logical_left_imm_64 = 105,
    shift_logical_right_imm_32 = 14,
    shift_logical_right_imm_64 = 106,
    shift_arithmetic_right_imm_32 = 25,
    shift_arithmetic_right_imm_64 = 107,
    negate_and_add_imm_32 = 40,
    negate_and_add_imm_64 = 136,
    set_greater_than_unsigned_imm = 39,
    set_greater_than_signed_imm = 61,
    shift_logical_right_imm_alt_32 = 72,
    shift_logical_right_imm_alt_64 = 103,
    shift_arithmetic_right_imm_alt_32 = 80,
    shift_arithmetic_right_imm_alt_64 = 111,
    shift_logical_left_imm_alt_32 = 75,
    shift_logical_left_imm_alt_64 = 110,
    cmov_if_zero_imm = 85,
    cmov_if_not_zero_imm = 86,
    rotate_right_32_imm = 158,
    rotate_right_32_imm_alt = 159,
    rotate_right_64_imm = 160,
    rotate_right_64_imm_alt = 161,
    branch_eq = 24,
    branch_not_eq = 30,
    branch_less_unsigned = 47,
    branch_less_signed = 48,
    branch_greater_or_equal_unsigned = 41,
    branch_greater_or_equal_signed = 43,
    add_32 = 8,
    add_64 = 101,
    sub_32 = 20,
    sub_64 = 112,
    and = 23,
    xor = 28,
    or = 12,
    mul_32 = 34,
    mul_64 = 113,
    mul_upper_signed_signed = 67,
    mul_upper_unsigned_unsigned = 57,
    mul_upper_signed_unsigned = 81,
    set_less_than_unsigned = 36,
    set_less_than_signed = 58,
    shift_logical_left_32 = 55,
    shift_logical_left_64 = 100,
    shift_logical_right_32 = 51,
    shift_logical_right_64 = 108,
    shift_arithmetic_right_32 = 77,
    shift_arithmetic_right_64 = 109,
    div_unsigned_32 = 68,
    div_unsigned_64 = 114,
    div_signed_32 = 64,
    div_signed_64 = 115,
    rem_unsigned_32 = 73,
    rem_unsigned_64 = 116,
    rem_signed_32 = 70,
    rem_signed_64 = 117,
    cmov_if_zero = 83,
    cmov_if_not_zero = 84,
    and_inverted = 162,
    or_inverted = 137,
    xnor = 138,
    maximum = 145,
    maximum_unsigned = 146,
    minimum = 147,
    minimum_unsigned = 148,
    rotate_left_32 = 152,
    rotate_left_64 = 153,
    rotate_right_32 = 154,
    rotate_right_64 = 155,
    jump = 5,
    ecalli = 78,
    store_imm_u8 = 62,
    store_imm_u16 = 79,
    store_imm_u32 = 38,
    store_imm_u64 = 98,
    move_reg = 82,
    sbrk = 87,
    count_leading_zero_bits_32 = 139,
    count_leading_zero_bits_64 = 140,
    count_trailing_zero_bits_32 = 141,
    count_trailing_zero_bits_64 = 142,
    count_set_bits_32 = 143,
    count_set_bits_64 = 144,
    sign_extend_8 = 149,
    sign_extend_16 = 150,
    zero_extend_16 = 151,
    or_combine_byte = 156,
    reverse_byte = 157,
    load_imm_and_jump_indirect = 42,
    load_imm64 = 118,
}