Struct Dhcsr

pub struct Dhcsr(pub u32);

Debug Halting Control and Status Register, DHCSR (see armv6-M Architecture Reference Manual C1.6.3)

To write this register successfully, you need to set the debug key via Dhcsr::enable_write first!

Tuple Fields

0: u32

Implementations

impl Dhcsr

pub fn s_reset_st(&self) -> bool

Indicates whether the processor has been reset since the last read of DHCSR:

0: No reset since last DHCSR read. 1: At least one reset since last DHCSR read.

This is a sticky bit, that clears to 0 on a read of DHCSR.

pub fn s_retire_st(&self) -> bool

When not in Debug state, indicates whether the processor has completed the execution of an instruction since the last read of DHCSR:

0: No instruction has completed since last DHCSR read. 1: At least one instructions has completed since last DHCSR read.

This is a sticky bit, that clears to 0 on a read of DHCSR.

This bit is UNKNOWN:

• after a Local reset, but is set to 1 as soon as the processor completes execution of an instruction.
• when S_LOCKUP is set to 1.
• when S_HALT is set to 1.

When the processor is not in Debug state, a debugger can check this bit to determine if the processor is stalled on a load, store or fetch access.

pub fn s_lockup(&self) -> bool

Indicates whether the processor is locked up because of an unrecoverable exception:

0: Not locked up.
1: Locked up.

See Unrecoverable exception cases on page B1-206 for more information.

This bit can only read as 1 when accessed by a remote debugger using the DAP. The value of 1 indicates that the processor is running but locked up.

The bit clears to 0 when the processor enters Debug state.

pub fn s_sleep(&self) -> bool

Indicates whether the processor is sleeping:

0: Not sleeping.
1: Sleeping.

The debugger must set the DHCSR.C_HALT bit to 1 to gain control, or wait for an interrupt or other wakeup event to wakeup the system

pub fn s_halt(&self) -> bool

Indicates whether the processor is in Debug state:

0: Not in Debug state.
1: In Debug state.

pub fn s_regrdy(&self) -> bool

A handshake flag for transfers through the DCRDR:

• Writing to DCRSR clears the bit to 0.
• Completion of the DCRDR transfer then sets the bit to 1.

For more information about DCRDR transfers see Debug Core Register Data Register, DCRDR on page C1-292.

0: There has been a write to the DCRDR, but the transfer is not complete.
1: The transfer to or from the DCRDR is complete.

This bit is only valid when the processor is in Debug state, otherwise the bit is UNKNOWN.

pub fn c_maskints(&self) -> bool

When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts:

0: Do not mask.
1: Mask PendSV, SysTick and external configurable interrupts.

The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both:

• before the write to DHCSR, the value of the C_HALT bit is 1.
• the write to the DHCSR that changes the C_MASKINTS bit also writes 1 to the C_HALT bit.

This means that a single write to DHCSR cannot set the C_HALT to 0 and change the value of the C_MASKINTS bit.

The bit does not affect NMI. When DHCSR.C_DEBUGEN is set to 0, the value of this bit is UNKNOWN.

For more information about the use of this bit see Table C1-9 on page C1-282.

This bit is UNKNOWN after a power-on reset.

pub fn c_step(&self) -> bool

Processor step bit. The effects of writes to this bit are:

0: Single-stepping disabled.
1: Single-stepping enabled.

For more information about the use of this bit see Table C1-9 on page C1-282.

This bit is UNKNOWN after a power-on reset.

pub fn c_halt(&self) -> bool

Processor halt bit. The effects of writes to this bit are:

0: Request a halted processor to run.
1: Request a running processor to halt.

Table C1-9 on page C1-282 shows the effect of writes to this bit when the processor is in Debug state.

This bit is 0 after a System reset.

pub fn c_debugen(&self) -> bool

Halting debug enable bit:

0: Halting debug disabled.
1: Halting debug enabled.

If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE.

This bit can only be written from the DAP. Access to the DHCSR from software running on the processor is IMPLEMENTATION DEFINED. However, writes to this bit from software running on the processor are ignored.

This bit is 0 after a power-on reset.

pub fn set_c_maskints(&mut self, value: bool)

When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts:

0: Do not mask.
1: Mask PendSV, SysTick and external configurable interrupts.

The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both:

• before the write to DHCSR, the value of the C_HALT bit is 1.
• the write to the DHCSR that changes the C_MASKINTS bit also writes 1 to the C_HALT bit.

This means that a single write to DHCSR cannot set the C_HALT to 0 and change the value of the C_MASKINTS bit.

The bit does not affect NMI. When DHCSR.C_DEBUGEN is set to 0, the value of this bit is UNKNOWN.

For more information about the use of this bit see Table C1-9 on page C1-282.

This bit is UNKNOWN after a power-on reset.

pub fn set_c_step(&mut self, value: bool)

Processor step bit. The effects of writes to this bit are:

0: Single-stepping disabled.
1: Single-stepping enabled.

For more information about the use of this bit see Table C1-9 on page C1-282.

This bit is UNKNOWN after a power-on reset.

pub fn set_c_halt(&mut self, value: bool)

Processor halt bit. The effects of writes to this bit are:

0: Request a halted processor to run.
1: Request a running processor to halt.

Table C1-9 on page C1-282 shows the effect of writes to this bit when the processor is in Debug state.

This bit is 0 after a System reset.

pub fn set_c_debugen(&mut self, value: bool)

Halting debug enable bit:

0: Halting debug disabled.
1: Halting debug enabled.

If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE.

This bit can only be written from the DAP. Access to the DHCSR from software running on the processor is IMPLEMENTATION DEFINED. However, writes to this bit from software running on the processor are ignored.

This bit is 0 after a power-on reset.

impl Dhcsr

pub fn enable_write(&mut self)

This function sets the bit to enable writes to this register.

Trait Implementations

impl<T> BitRange<T> for Dhcsr

where u32: BitRange<T>,

fn bit_range(&self, msb: usize, lsb: usize) -> T

Get a range of bits.

impl<T> BitRangeMut<T> for Dhcsr

where u32: BitRangeMut<T>,

fn set_bit_range(&mut self, msb: usize, lsb: usize, value: T)

Set a range of bits.

impl Clone for Dhcsr

fn clone(&self) -> Dhcsr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Dhcsr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<Dhcsr> for u32

fn from(value: Dhcsr) -> Self

Converts to this type from the input type.

impl From<u32> for Dhcsr

fn from(value: u32) -> Self

Converts to this type from the input type.

impl MemoryMappedRegister<u32> for Dhcsr

const ADDRESS_OFFSET: u64 = 3_758_157_296u64

The register’s address in the target memory. For some architectures (e.g. ARM Cortex-A) this address is offset from a base address. For others (e.g. ARM Cortex-M, RISC-V) this address is absolute.

const NAME: &'static str = "DHCSR"

The register’s name.

fn get_mmio_address_from_base( base_address: u64, ) -> Result<u64, RegisterAddressOutOfBounds>

Get the register’s address in the memory map. For architectures like ARM Cortex-A, this address is offset from a base address, which must be supplied when calling this method. For others (e.g. ARM Cortex-M, RISC-V) where this address is a constant, please use MemoryMappedRegister::get_mmio_address.

fn get_mmio_address() -> u64

Get the register’s address in the memory map. For architectures ARM Cortex-M and RISC-V, this address is constant value stored as part of MemoryMappedRegister::ADDRESS_OFFSET. For other architectures (e.g. ARM Cortex-A) where this address is offset from a base address, please use MemoryMappedRegister::get_mmio_address_from_base.

impl Copy for Dhcsr