probe_rs::architecture::riscv::communication_interface

Enum RiscvError

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pub enum RiscvError {

Show 18 variants    DtmOperationFailed,
    DtmOperationInProcess,
    DebugProbe(DebugProbeError),
    Timeout,
    AbstractCommand(AbstractCommandErrorKind),
    RequestNotAcknowledged,
    UnsupportedDebugTransportModuleVersion(u8),
    UnsupportedDebugModuleVersion(DebugModuleVersion),
    UnsupportedCsrAddress(u16),
    UnsupportedProgramBufferRegister(usize),
    ProgramBufferTooSmall,
    UnsupportedBusAccessWidth(RiscvBusAccess),
    SystemBusAccess,
    UnexpectedTriggerType(u32),
    NoRiscvTarget,
    ResetHaltRequestNotSupported,
    BatchedResultNotAvailable,
    HartUnavailable,

}
Expand description

Some error occurred when working with the RISC-V core.

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DtmOperationFailed

An error occurred during transport

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DtmOperationInProcess

DMI operation is in progress

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DebugProbe(DebugProbeError)

An error with operating the debug probe occurred.

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Timeout

A timeout occurred during DMI access.

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AbstractCommand(AbstractCommandErrorKind)

An error occurred during the execution of an abstract command.

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RequestNotAcknowledged

The request for reset, resume or halt was not acknowledged.

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UnsupportedDebugTransportModuleVersion(u8)

This debug transport module (DTM) version is currently not supported.

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UnsupportedDebugModuleVersion(DebugModuleVersion)

This version of the debug module is not supported.

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UnsupportedCsrAddress(u16)

The provided csr address was invalid/unsupported

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UnsupportedProgramBufferRegister(usize)

The given program buffer register is not supported.

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ProgramBufferTooSmall

The program buffer is too small for the supplied program.

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UnsupportedBusAccessWidth(RiscvBusAccess)

Memory width larger than 32 bits is not supported yet.

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SystemBusAccess

An error during system bus access occurred.

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UnexpectedTriggerType(u32)

The given trigger type is not available for the address breakpoint.

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NoRiscvTarget

The connected target is not a RISC-V device.

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ResetHaltRequestNotSupported

The target does not support halt after reset.

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BatchedResultNotAvailable

The result index of a batched command is not available.

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HartUnavailable

The hart is unavailable

Trait Implementations§

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impl Debug for RiscvError

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl Display for RiscvError

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fn fmt(&self, __formatter: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl Error for RiscvError

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fn source(&self) -> Option<&(dyn Error + 'static)>

Returns the lower-level source of this error, if any. Read more
1.0.0 · Source§

fn description(&self) -> &str

👎Deprecated since 1.42.0: use the Display impl or to_string()
Read more
1.0.0 · Source§

fn cause(&self) -> Option<&dyn Error>

👎Deprecated since 1.33.0: replaced by Error::source, which can support downcasting
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fn provide<'a>(&'a self, request: &mut Request<'a>)

🔬This is a nightly-only experimental API. (error_generic_member_access)
Provides type-based access to context intended for error reports. Read more
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impl From<AbstractCommandErrorKind> for RiscvError

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fn from(err: AbstractCommandErrorKind) -> Self

Converts to this type from the input type.
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impl From<DebugProbeError> for RiscvError

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fn from(source: DebugProbeError) -> Self

Converts to this type from the input type.
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impl From<RiscvError> for Error

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fn from(err: RiscvError) -> Self

Converts to this type from the input type.

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