pub enum Error {
Show 18 variants
Probe(DebugProbeError),
Arm(ArmError),
Riscv(RiscvError),
Xtensa(XtensaError),
CoreDisabled(usize),
CoreNotFound(usize),
ChipNotFound(RegistryError),
MissingPermissions(String),
GenericCoreError(String),
Register(String),
RegisterAddressOutOfBounds(RegisterAddressOutOfBounds),
NotImplemented(&'static str),
Other(String),
Timeout,
MemoryNotAligned(MemoryNotAlignedError),
InvalidDataLength(InvalidDataLengthError),
WriteRegister {
register: String,
source: Box<dyn Error + Send + Sync + 'static>,
},
ReadRegister {
register: String,
source: Box<dyn Error + Send + Sync + 'static>,
},
}
Expand description
The overarching error type which contains all possible errors as variants.
Variants§
Probe(DebugProbeError)
An error with the usage of the probe occurred
Arm(ArmError)
An ARM specific error occurred.
Riscv(RiscvError)
A RISC-V specific error occurred.
Xtensa(XtensaError)
An Xtensa specific error occurred.
CoreDisabled(usize)
Core {0} is not enabled.
CoreNotFound(usize)
Core {0} does not exist.
ChipNotFound(RegistryError)
Unable to load specification for chip
MissingPermissions(String)
An operation was not performed because the required permissions were not given: {0}.
This can for example happen when the core is locked and needs to be erased to be unlocked. Then the correct permission needs to be given to automatically unlock the core to prevent accidental erases.
GenericCoreError(String)
An error that is not architecture specific occurred: {0}
Register(String)
Errors accessing core register: {0}
RegisterAddressOutOfBounds(RegisterAddressOutOfBounds)
Error calculating the address of a register
NotImplemented(&'static str)
The {0} capability has not yet been implemented for this architecture.
Because of the large varieties of supported architectures, it is not always possible for a contributor to implement functionality for all of them. This allows us to implement new functionality on selected architectures first, and then add support for the other architectures later.
Other(String)
Some uncategorized error occurred.
Timeout
A timeout occurred.
MemoryNotAligned(MemoryNotAlignedError)
Memory access to address {0.address:#X?} was not aligned to {0.alignment} bytes.
InvalidDataLength(InvalidDataLengthError)
The data buffer had an invalid length.
WriteRegister
Failed to write CPU register {register}.
Fields
ReadRegister
Failed to read CPU register {register}.
Trait Implementations§
Source§impl Error for Error
impl Error for Error
Source§fn source(&self) -> Option<&(dyn Error + 'static)>
fn source(&self) -> Option<&(dyn Error + 'static)>
1.0.0 · Source§fn description(&self) -> &str
fn description(&self) -> &str
Source§impl From<DebugProbeError> for Error
impl From<DebugProbeError> for Error
Source§fn from(source: DebugProbeError) -> Self
fn from(source: DebugProbeError) -> Self
Source§impl From<Error> for DebugError
Available on crate feature debug
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impl From<Error> for DebugError
debug
only.Source§impl From<Error> for FileDownloadError
impl From<Error> for FileDownloadError
Source§impl From<RegistryError> for Error
impl From<RegistryError> for Error
Source§fn from(source: RegistryError) -> Self
fn from(source: RegistryError) -> Self
Source§impl From<RiscvError> for Error
impl From<RiscvError> for Error
Source§fn from(err: RiscvError) -> Self
fn from(err: RiscvError) -> Self
Source§impl From<XtensaError> for Error
impl From<XtensaError> for Error
Source§fn from(err: XtensaError) -> Self
fn from(err: XtensaError) -> Self
Auto Trait Implementations§
impl Freeze for Error
impl !RefUnwindSafe for Error
impl Send for Error
impl Sync for Error
impl Unpin for Error
impl !UnwindSafe for Error
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