Struct raw_cpuid::ExtendedFeatures

pub struct ExtendedFeatures { /* private fields */ }

Structured Extended Feature Identifiers (LEAF=0x07).

Platforms

🟡 AMD ✅ Intel

Implementations

impl ExtendedFeatures

pub const fn has_fsgsbase(&self) -> bool

FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.

Platforms

✅ AMD ✅ Intel

pub const fn has_tsc_adjust_msr(&self) -> bool

IA32_TSC_ADJUST MSR is supported if 1.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_bmi1(&self) -> bool

BMI1

Platforms

✅ AMD ✅ Intel

pub const fn has_hle(&self) -> bool

HLE

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_avx2(&self) -> bool

AVX2

Platforms

✅ AMD ✅ Intel

pub const fn has_fdp(&self) -> bool

FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if 1.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_smep(&self) -> bool

SMEP. Supports Supervisor-Mode Execution Prevention if 1.

Platforms

✅ AMD ✅ Intel

pub const fn has_bmi2(&self) -> bool

BMI2

Platforms

✅ AMD ✅ Intel

pub const fn has_rep_movsb_stosb(&self) -> bool

Supports Enhanced REP MOVSB/STOSB if 1.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_invpcid(&self) -> bool

INVPCID. If 1, supports INVPCID instruction for system software that manages process-context identifiers.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_rtm(&self) -> bool

RTM

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_rdtm(&self) -> bool

Supports Intel Resource Director Technology (RDT) Monitoring capability.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_fpu_cs_ds_deprecated(&self) -> bool

Deprecates FPU CS and FPU DS values if 1.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_mpx(&self) -> bool

MPX. Supports Intel Memory Protection Extensions if 1.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_rdta(&self) -> bool

Supports Intel Resource Director Technology (RDT) Allocation capability.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_rdseed(&self) -> bool

Supports RDSEED.

Platforms

✅ AMD ✅ Intel

pub const fn has_adx(&self) -> bool

Supports ADX.

Platforms

✅ AMD ✅ Intel

pub const fn has_smap(&self) -> bool

SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1.

Platforms

✅ AMD ✅ Intel

pub const fn has_clflushopt(&self) -> bool

Supports CLFLUSHOPT.

Platforms

✅ AMD ✅ Intel

pub const fn has_processor_trace(&self) -> bool

Supports Intel Processor Trace.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_sha(&self) -> bool

Supports SHA Instructions.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_sgx(&self) -> bool

Supports Intel® Software Guard Extensions (Intel® SGX Extensions).

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_avx512f(&self) -> bool

Supports AVX512F.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_avx512dq(&self) -> bool

Supports AVX512DQ.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_avx512_ifma(&self) -> bool

AVX512_IFMA

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_avx512pf(&self) -> bool

AVX512PF

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_avx512er(&self) -> bool

AVX512ER

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_avx512cd(&self) -> bool

AVX512CD

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_avx512bw(&self) -> bool

AVX512BW

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_avx512vl(&self) -> bool

AVX512VL

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_clwb(&self) -> bool

CLWB

Platforms

✅ AMD ✅ Intel

pub const fn has_prefetchwt1(&self) -> bool

Has PREFETCHWT1 (Intel® Xeon Phi™ only).

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_umip(&self) -> bool

Supports user-mode instruction prevention if 1.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_pku(&self) -> bool

Supports protection keys for user-mode pages.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_ospke(&self) -> bool

OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instructions.

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_waitpkg(&self) -> bool

WAITPKG

❓ AMD ✅ Intel

pub const fn has_av512vbmi2(&self) -> bool

AVX512VBMI2

❓ AMD ✅ Intel

pub const fn has_cet_ss(&self) -> bool

Supports CET shadow stack features. Processors that set this bit define bits 0..2 of the IA32_U_CET and IA32_S_CET MSRs. Enumerates support for the following MSRs: IA32_INTERRUPT_SPP_TABLE_ADDR, IA32_PL3_SSP, IA32_PL2_SSP, IA32_PL1_SSP, and IA32_PL0_SSP.

❓ AMD ✅ Intel

pub const fn has_gfni(&self) -> bool

GFNI

❓ AMD ✅ Intel

pub const fn has_vaes(&self) -> bool

VAES

❓ AMD ✅ Intel

pub const fn has_vpclmulqdq(&self) -> bool

VPCLMULQDQ

❓ AMD ✅ Intel

pub const fn has_avx512vnni(&self) -> bool

AVX512VNNI

Platforms

❌ AMD (reserved) ✅ Intel

pub const fn has_avx512bitalg(&self) -> bool

AVX512BITALG

❓ AMD ✅ Intel

pub const fn has_tme_en(&self) -> bool

Indicates the following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.

❓ AMD ✅ Intel

pub const fn has_avx512vpopcntdq(&self) -> bool

AVX512VPOPCNTDQ

❓ AMD ✅ Intel

pub const fn has_la57(&self) -> bool

Supports 57-bit linear addresses and five-level paging if 1.

Platforms

❓ AMD ✅ Intel

pub const fn has_rdpid(&self) -> bool

RDPID and IA32_TSC_AUX are available.

Bug

The Intel manual lists RDPID as bit 22 in the ECX register, but AMD lists it as bit 22 in the ebx register. We assumed that the AMD manual was wrong and query ecx, let’s see what happens.

Platforms

✅ AMD ✅ Intel

pub const fn has_sgx_lc(&self) -> bool

Supports SGX Launch Configuration.

Platforms

❌ AMD (reserved) ✅ Intel

pub fn mawau_value(&self) -> u8

The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.

Platforms

❌ AMD (reserved) ✅ Intel

Trait Implementations

impl Debug for ExtendedFeatures

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.