Struct raw_cpuid::DatInfo [−][src]
pub struct DatInfo { /* fields omitted */ }
Expand description
Deterministic Address Translation Structure
Implementations
4K page size entries supported by this structure
2MB page size entries supported by this structure
4MB page size entries supported by this structure
1GB page size entries supported by this structure
Fully associative structure
Partitioning (0: Soft partitioning between the logical processors sharing this structure).
Translation cache type field.
Translation cache level (starts at 1)
Maximum number of addressable IDs for logical processors sharing this translation cache