Struct raw_cpuid::ProcessorTraceInfo

pub struct ProcessorTraceInfo { /* fields omitted */ }

Implementations

impl ProcessorTraceInfo

pub fn has_rtit_cr3_match(&self) -> bool

If true, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that IA32_RTIT_CR3_MATCH MSR can be accessed.

pub fn has_configurable_psb_and_cycle_accurate_mode(&self) -> bool

If true, Indicates support of Configurable PSB and Cycle-Accurate Mode.

pub fn has_ip_tracestop_filtering(&self) -> bool

If true, Indicates support of IP Filtering, TraceStop filtering, and preservation of Intel PT MSRs across warm reset.

pub fn has_mtc_timing_packet_coefi_suppression(&self) -> bool

If true, Indicates support of MTC timing packet and suppression of COFI-based packets.

pub fn has_ptwrite(&self) -> bool

Indicates support of PTWRITE. Writes can set IA32_RTIT_CTL[12] (PTWEn and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE can generate packets

pub fn has_power_event_trace(&self) -> bool

Support of Power Event Trace. Writes can set IA32_RTIT_CTL[4] (PwrEvtEn) enabling Power Event Trace packet generation.

pub fn has_topa(&self) -> bool

If true, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.

pub fn has_topa_maximum_entries(&self) -> bool

If true, ToPA tables can hold any number of output entries, up to the maximum allowed by the MaskOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.

pub fn has_single_range_output_scheme(&self) -> bool

If true, Indicates support of Single-Range Output scheme.

pub fn has_trace_transport_subsystem(&self) -> bool

If true, Indicates support of output to Trace Transport subsystem.

pub fn has_lip_with_cs_base(&self) -> bool

If true, Generated packets which contain IP payloads have LIP values, which include the CS base component.

pub fn configurable_address_ranges(&self) -> u8

Number of configurable Address Ranges for filtering (Bits 2:0).

pub fn supported_mtc_period_encodings(&self) -> u16

Bitmap of supported MTC period encodings (Bit 31:16).

pub fn supported_cycle_threshold_value_encodings(&self) -> u16

Bitmap of supported Cycle Threshold value encodings (Bits 15-0).

pub fn supported_psb_frequency_encodings(&self) -> u16

Bitmap of supported Configurable PSB frequency encodings (Bit 31:16)

Trait Implementations

impl Debug for ProcessorTraceInfo

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for ProcessorTraceInfo

fn default() -> ProcessorTraceInfo

Returns the “default value” for a type.