Expand description
Hardware Abstraction Layer for STM32 Memory Controllers (FMC/FSMC)
§Implementation Guide
You can use the functionality in this crate by implementing the
FmcPeripheral trait. You should implement this trait for a
structure that:
- Takes ownership of the
FMC/FSMCperipheral - Takes ownership of any structures / ZSTs related to the power or clock for the
FMC/FSMCperipheral - Contains the frequency of the
FMC/FSMCsource clock (usually HCLK)
A basic structure:
pub struct FMC {
source_clock: u32,
// any other fields here...
}An implementation of FmcPeripheral:
use stm32_fmc::FmcPeripheral;
unsafe impl Sync for FMC {}
unsafe impl FmcPeripheral for FMC {
const REGISTERS: *const () = stm32::FMC::ptr() as *const ();
fn enable(&mut self) {
// Enable and reset the FMC/FSMC using the RCC registers
// Typically RCC.AHBxEN and RCC.AHBxRST
}
fn memory_controller_enable(&mut self) {
// Only required if your part has an `FMCEN` bit
}
fn source_clock_hz(&self) -> u32 {
self.source_clock
}
}In a HAL, you can allow users to construct your structure by implementing a
new method, or by making the fields public.
§Wrap constructor methods
Each memory controller type (Sdram, Nand, ..) provides both
new and new_unchecked methods.
For the convenience of users, you may want to wrap these with your new method,
so that each memory can be created from the peripheral in one step.
use stm32_fmc::{
AddressPinSet, PinsSdram, Sdram, SdramChip, SdramPinSet, SdramTargetBank,
};
impl FMC {
/// A new SDRAM memory via the Flexible Memory Controller
pub fn sdram<
BANK: SdramPinSet,
ADDR: AddressPinSet,
PINS: PinsSdram<BANK, ADDR>,
CHIP: SdramChip,
>(
fmc: stm32::FMC,
pins: PINS,
chip: CHIP,
clocks: &CoreClocks,
) -> Sdram<FMC, CHIP> {
let fmc = Self::new(fmc, clocks);
Sdram::new(fmc, pins, chip)
}
/// A new SDRAM memory via the Flexible Memory Controller
pub fn sdram_unchecked<CHIP: SdramChip, BANK: Into<SdramTargetBank>>(
fmc: stm32::FMC,
bank: BANK,
chip: CHIP,
clocks: &CoreClocks,
) -> Sdram<FMC, CHIP> {
let fmc = Self::new(fmc, clocks);
Sdram::new_unchecked(fmc, bank, chip)
}
}§Pin implementations
In contrast with the new_unchecked methods, the new methods require the user
pass a tuple as the pins argument. In a HAL, you can mark which types are
suitable as follows:
impl stm32_fmc::A0 for gpiof::PF0<Alternate<AF12>> {}
// ...Modules§
- Memory device definitions
- Management of external NAND Flash through the STM32 FMC peripheral
Macros§
- Modify a RWRegister or UnsafeRWRegister.
- Read the value from a RORegister, RWRegister, UnsafeRORegister, or UnsafeRWRegister.
- Reset a RWRegister, UnsafeRWRegister, WORegister, or UnsafeWORegister to its reset value.
- Write to a RWRegister or UnsafeRWRegister.
Structs§
- Type to mark that there are 11 address pins
- Type to mark that there are 12 address pins
- Type to mark that there are 13 address pins
- FMC Peripheral specialized as a NAND Controller. Not yet initialized.
- FMC NAND Physical Interface Configuration
- FMC NAND Timing parameters
- SDRAM Controller
- FMC SDRAM Configuration Structure definition
- FMC SDRAM Timing parameters structure definition
Enums§
- FMC banks
- Target bank for SDRAM commands
Traits§
- Marks a type as an A0 pin
- Marks a type as an A1 pin
- Marks a type as an A2 pin
- Marks a type as an A3 pin
- Marks a type as an A4 pin
- Marks a type as an A5 pin
- Marks a type as an A6 pin
- Marks a type as an A7 pin
- Marks a type as an A8 pin
- Marks a type as an A9 pin
- Marks a type as an A10 pin
- Marks a type as an A11 pin
- Marks a type as an A12 pin
- Marks a type as an A13 pin
- Marks a type as an A14 pin
- Marks a type as an A15 pin
- Marks a type as an A16 pin
- Marks a type as an A17 pin
- Marks a type as an A18 pin
- Marks a type as an A19 pin
- Marks a type as an A20 pin
- Marks a type as an A21 pin
- Marks a type as an A22 pin
- Marks a type as an A23 pin
- Marks a type as an A24 pin
- Marks a type as an A25 pin
- Set of address pins
- Marks a type as a BA0 pin
- Marks a type as a BA1 pin
- Marks a type as a CLK pin
- Marks a type as a D0 pin
- Marks a type as a D1 pin
- Marks a type as a D2 pin
- Marks a type as a D3 pin
- Marks a type as a D4 pin
- Marks a type as a D5 pin
- Marks a type as a D6 pin
- Marks a type as a D7 pin
- Marks a type as a D8 pin
- Marks a type as a D9 pin
- Marks a type as a D10 pin
- Marks a type as a D11 pin
- Marks a type as a D12 pin
- Marks a type as a D13 pin
- Marks a type as a D14 pin
- Marks a type as a D15 pin
- Marks a type as a D16 pin
- Marks a type as a D17 pin
- Marks a type as a D18 pin
- Marks a type as a D19 pin
- Marks a type as a D20 pin
- Marks a type as a D21 pin
- Marks a type as a D22 pin
- Marks a type as a D23 pin
- Marks a type as a D24 pin
- Marks a type as a D25 pin
- Marks a type as a D26 pin
- Marks a type as a D27 pin
- Marks a type as a D28 pin
- Marks a type as a D29 pin
- Marks a type as a D30 pin
- Marks a type as a D31 pin
- Marks a type as a DA0 pin
- Marks a type as a DA1 pin
- Marks a type as a DA2 pin
- Marks a type as a DA3 pin
- Marks a type as a DA4 pin
- Marks a type as a DA5 pin
- Marks a type as a DA6 pin
- Marks a type as a DA7 pin
- Marks a type as a DA8 pin
- Marks a type as a DA9 pin
- Marks a type as a DA10 pin
- Marks a type as a DA11 pin
- Marks a type as a DA12 pin
- Marks a type as a DA13 pin
- Marks a type as a DA14 pin
- Marks a type as a DA15 pin
- A trait for device-specific FMC peripherals. Implement this to add support for a new hardware platform. Peripherals that have this trait must have the same register block as STM32 FMC peripherals.
- Marks a type as an INT pin
- Marks a type as a NBL0 pin
- Marks a type as a NBL1 pin
- Marks a type as a NBL2 pin
- Marks a type as a NBL3 pin
- Marks a type as a NCE pin
- Marks a type as a NE1 pin
- Marks a type as a NE2 pin
- Marks a type as a NE3 pin
- Marks a type as a NE4 pin
- Marks a type as a NL pin
- Marks a type as a NOE pin
- Marks a type as a NWAIT pin
- Marks a type as a NWE pin
- Respresents a model of NAND chip
- Set of pins for a NAND
- Set of pins for an SDRAM, that corresponds to a specific bank
- Marks a type as a SDCKE0 pin
- Marks a type as a SDCKE1 pin
- Marks a type as a SDCLK pin
- Marks a type as a SDNCAS pin
- Marks a type as a SDNE0 pin
- Marks a type as a SDNE1 pin
- Marks a type as a SDNRAS pin
- Marks a type as a SDNWE pin
- Respresents a model of SDRAM chip
- SDRAM target bank and corresponding FMC Bank