Crate stm32_fmc

Expand description

Hardware Abstraction Layer for STM32 Memory Controllers (FMC/FSMC)

§Implementation Guide

You can use the functionality in this crate by implementing the FmcPeripheral trait. You should implement this trait for a structure that:

Takes ownership of the FMC/FSMC peripheral
Takes ownership of any structures / ZSTs related to the power or clock for the FMC/FSMC peripheral
Contains the frequency of the FMC/FSMC source clock (usually HCLK)

A basic structure:

pub struct FMC {
    source_clock: u32,
    // any other fields here...
}

An implementation of FmcPeripheral:

use stm32_fmc::FmcPeripheral;

unsafe impl Sync for FMC {}
unsafe impl FmcPeripheral for FMC {
    const REGISTERS: *const () = stm32::FMC::ptr() as *const ();

    fn enable(&mut self) {
        // Enable and reset the FMC/FSMC using the RCC registers
        // Typically RCC.AHBxEN and RCC.AHBxRST
    }

    fn memory_controller_enable(&mut self) {
        // Only required if your part has an `FMCEN` bit
    }

    fn source_clock_hz(&self) -> u32 {
        self.source_clock
    }
}

In a HAL, you can allow users to construct your structure by implementing a new method, or by making the fields public.

§Wrap constructor methods

Each memory controller type (Sdram, Nand, ..) provides both new and new_unchecked methods.

For the convenience of users, you may want to wrap these with your new method, so that each memory can be created from the peripheral in one step.

use stm32_fmc::{
    AddressPinSet, PinsSdram, Sdram, SdramChip, SdramPinSet, SdramTargetBank,
};

impl FMC {
    /// A new SDRAM memory via the Flexible Memory Controller
    pub fn sdram<
        BANK: SdramPinSet,
        ADDR: AddressPinSet,
        PINS: PinsSdram<BANK, ADDR>,
        CHIP: SdramChip,
    >(
        fmc: stm32::FMC,
        pins: PINS,
        chip: CHIP,
        clocks: &CoreClocks,
    ) -> Sdram<FMC, CHIP> {
        let fmc = Self::new(fmc, clocks);
        Sdram::new(fmc, pins, chip)
    }

    /// A new SDRAM memory via the Flexible Memory Controller
    pub fn sdram_unchecked<CHIP: SdramChip, BANK: Into<SdramTargetBank>>(
        fmc: stm32::FMC,
        bank: BANK,
        chip: CHIP,
        clocks: &CoreClocks,
    ) -> Sdram<FMC, CHIP> {
        let fmc = Self::new(fmc, clocks);
        Sdram::new_unchecked(fmc, bank, chip)
    }
}

§Pin implementations

In contrast with the new_unchecked methods, the new methods require the user pass a tuple as the pins argument. In a HAL, you can mark which types are suitable as follows:

impl stm32_fmc::A0 for gpiof::PF0<Alternate<AF12>> {}
// ...

Modules§

devices: Memory device definitions
nand_device: Management of external NAND Flash through the STM32 FMC peripheral

Macros§

modify_reg: Modify a RWRegister or UnsafeRWRegister.
read_reg: Read the value from a RORegister, RWRegister, UnsafeRORegister, or UnsafeRWRegister.
reset_reg: Reset a RWRegister, UnsafeRWRegister, WORegister, or UnsafeWORegister to its reset value.
write_reg: Write to a RWRegister or UnsafeRWRegister.

Structs§

AddressPins11: Type to mark that there are 11 address pins
AddressPins12: Type to mark that there are 12 address pins
AddressPins13: Type to mark that there are 13 address pins
Nand: FMC Peripheral specialized as a NAND Controller. Not yet initialized.
NandConfiguration: FMC NAND Physical Interface Configuration
NandTiming: FMC NAND Timing parameters
Sdram: SDRAM Controller
SdramConfiguration: FMC SDRAM Configuration Structure definition
SdramTiming: FMC SDRAM Timing parameters structure definition

Enums§

FmcBank: FMC banks
SdramTargetBank: Target bank for SDRAM commands

Traits§

A0: Marks a type as an A0 pin
A1: Marks a type as an A1 pin
A2: Marks a type as an A2 pin
A3: Marks a type as an A3 pin
A4: Marks a type as an A4 pin
A5: Marks a type as an A5 pin
A6: Marks a type as an A6 pin
A7: Marks a type as an A7 pin
A8: Marks a type as an A8 pin
A9: Marks a type as an A9 pin
A10: Marks a type as an A10 pin
A11: Marks a type as an A11 pin
A12: Marks a type as an A12 pin
A13: Marks a type as an A13 pin
A14: Marks a type as an A14 pin
A15: Marks a type as an A15 pin
A16: Marks a type as an A16 pin
A17: Marks a type as an A17 pin
A18: Marks a type as an A18 pin
A19: Marks a type as an A19 pin
A20: Marks a type as an A20 pin
A21: Marks a type as an A21 pin
A22: Marks a type as an A22 pin
A23: Marks a type as an A23 pin
A24: Marks a type as an A24 pin
A25: Marks a type as an A25 pin
AddressPinSet: Set of address pins
BA0: Marks a type as a BA0 pin
BA1: Marks a type as a BA1 pin
CLK: Marks a type as a CLK pin
D0: Marks a type as a D0 pin
D1: Marks a type as a D1 pin
D2: Marks a type as a D2 pin
D3: Marks a type as a D3 pin
D4: Marks a type as a D4 pin
D5: Marks a type as a D5 pin
D6: Marks a type as a D6 pin
D7: Marks a type as a D7 pin
D8: Marks a type as a D8 pin
D9: Marks a type as a D9 pin
D10: Marks a type as a D10 pin
D11: Marks a type as a D11 pin
D12: Marks a type as a D12 pin
D13: Marks a type as a D13 pin
D14: Marks a type as a D14 pin
D15: Marks a type as a D15 pin
D16: Marks a type as a D16 pin
D17: Marks a type as a D17 pin
D18: Marks a type as a D18 pin
D19: Marks a type as a D19 pin
D20: Marks a type as a D20 pin
D21: Marks a type as a D21 pin
D22: Marks a type as a D22 pin
D23: Marks a type as a D23 pin
D24: Marks a type as a D24 pin
D25: Marks a type as a D25 pin
D26: Marks a type as a D26 pin
D27: Marks a type as a D27 pin
D28: Marks a type as a D28 pin
D29: Marks a type as a D29 pin
D30: Marks a type as a D30 pin
D31: Marks a type as a D31 pin
DA0: Marks a type as a DA0 pin
DA1: Marks a type as a DA1 pin
DA2: Marks a type as a DA2 pin
DA3: Marks a type as a DA3 pin
DA4: Marks a type as a DA4 pin
DA5: Marks a type as a DA5 pin
DA6: Marks a type as a DA6 pin
DA7: Marks a type as a DA7 pin
DA8: Marks a type as a DA8 pin
DA9: Marks a type as a DA9 pin
DA10: Marks a type as a DA10 pin
DA11: Marks a type as a DA11 pin
DA12: Marks a type as a DA12 pin
DA13: Marks a type as a DA13 pin
DA14: Marks a type as a DA14 pin
DA15: Marks a type as a DA15 pin
FmcPeripheral: A trait for device-specific FMC peripherals. Implement this to add support for a new hardware platform. Peripherals that have this trait must have the same register block as STM32 FMC peripherals.
INT: Marks a type as an INT pin
NBL0: Marks a type as a NBL0 pin
NBL1: Marks a type as a NBL1 pin
NBL2: Marks a type as a NBL2 pin
NBL3: Marks a type as a NBL3 pin
NCE: Marks a type as a NCE pin
NE1: Marks a type as a NE1 pin
NE2: Marks a type as a NE2 pin
NE3: Marks a type as a NE3 pin
NE4: Marks a type as a NE4 pin
NL: Marks a type as a NL pin
NOE: Marks a type as a NOE pin
NWAIT: Marks a type as a NWAIT pin
NWE: Marks a type as a NWE pin
NandChip: Respresents a model of NAND chip
PinsNand: Set of pins for a NAND
PinsSdram: Set of pins for an SDRAM, that corresponds to a specific bank
SDCKE0: Marks a type as a SDCKE0 pin
SDCKE1: Marks a type as a SDCKE1 pin
SDCLK: Marks a type as a SDCLK pin
SDNCAS: Marks a type as a SDNCAS pin
SDNE0: Marks a type as a SDNE0 pin
SDNE1: Marks a type as a SDNE1 pin
SDNRAS: Marks a type as a SDNRAS pin
SDNWE: Marks a type as a SDNWE pin
SdramChip: Respresents a model of SDRAM chip
SdramPinSet: SDRAM target bank and corresponding FMC Bank

Crate stm32_fmcCopy item path