Struct stm32_metapac::pwr::regs::D3cr
#[repr(transparent)]pub struct D3cr(pub u32);
Expand description
This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software
Tuple Fields§
§0: u32
Implementations§
§impl D3cr
impl D3cr
pub const fn vosrdy(&self) -> bool
pub const fn vosrdy(&self) -> bool
VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3).
pub fn set_vosrdy(&mut self, val: bool)
pub fn set_vosrdy(&mut self, val: bool)
VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3).
pub const fn vos(&self) -> Vos
pub const fn vos(&self) -> Vos
Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.
pub fn set_vos(&mut self, val: Vos)
pub fn set_vos(&mut self, val: Vos)
Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.