Enum Instruction

#[repr(u16)]
pub enum Instruction {
    Trap {
        trap_code: TrapCode,
    },
    ConsumeFuel {
        block_fuel: BlockFuel,
    },
    Return,
    ReturnReg {
        value: Reg,
    },
    ReturnReg2 {
        values: [Reg; 2],
    },
    ReturnReg3 {
        values: [Reg; 3],
    },
    ReturnImm32 {
        value: AnyConst32,
    },
    ReturnI64Imm32 {
        value: Const32<i64>,
    },
    ReturnF64Imm32 {
        value: Const32<f64>,
    },
    ReturnSpan {
        values: BoundedRegSpan,
    },
    ReturnMany {
        values: [Reg; 3],
    },
    ReturnNez {
        condition: Reg,
    },
    ReturnNezReg {
        condition: Reg,
        value: Reg,
    },
    ReturnNezReg2 {
        condition: Reg,
        values: [Reg; 2],
    },
    ReturnNezImm32 {
        condition: Reg,
        value: AnyConst32,
    },
    ReturnNezI64Imm32 {
        condition: Reg,
        value: Const32<i64>,
    },
    ReturnNezF64Imm32 {
        condition: Reg,
        value: Const32<f64>,
    },
    ReturnNezSpan {
        condition: Reg,
        values: BoundedRegSpan,
    },
    ReturnNezMany {
        condition: Reg,
        values: [Reg; 2],
    },
    Branch {
        offset: BranchOffset,
    },
    BranchCmpFallback {
        lhs: Reg,
        rhs: Reg,
        params: Reg,
    },
    BranchI32And {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32AndImm16 {
        lhs: Reg,
        rhs: Const16<i32>,
        offset: BranchOffset16,
    },
    BranchI32Or {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32OrImm16 {
        lhs: Reg,
        rhs: Const16<i32>,
        offset: BranchOffset16,
    },
    BranchI32Xor {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32XorImm16 {
        lhs: Reg,
        rhs: Const16<i32>,
        offset: BranchOffset16,
    },
    BranchI32AndEqz {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32AndEqzImm16 {
        lhs: Reg,
        rhs: Const16<i32>,
        offset: BranchOffset16,
    },
    BranchI32OrEqz {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32OrEqzImm16 {
        lhs: Reg,
        rhs: Const16<i32>,
        offset: BranchOffset16,
    },
    BranchI32XorEqz {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32XorEqzImm16 {
        lhs: Reg,
        rhs: Const16<i32>,
        offset: BranchOffset16,
    },
    BranchI32Eq {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32EqImm16 {
        lhs: Reg,
        rhs: Const16<i32>,
        offset: BranchOffset16,
    },
    BranchI32Ne {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32NeImm16 {
        lhs: Reg,
        rhs: Const16<i32>,
        offset: BranchOffset16,
    },
    BranchI32LtS {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32LtSImm16Lhs {
        lhs: Const16<i32>,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32LtSImm16Rhs {
        lhs: Reg,
        rhs: Const16<i32>,
        offset: BranchOffset16,
    },
    BranchI32LtU {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32LtUImm16Lhs {
        lhs: Const16<u32>,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32LtUImm16Rhs {
        lhs: Reg,
        rhs: Const16<u32>,
        offset: BranchOffset16,
    },
    BranchI32LeS {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32LeSImm16Lhs {
        lhs: Const16<i32>,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32LeSImm16Rhs {
        lhs: Reg,
        rhs: Const16<i32>,
        offset: BranchOffset16,
    },
    BranchI32LeU {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32LeUImm16Lhs {
        lhs: Const16<u32>,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI32LeUImm16Rhs {
        lhs: Reg,
        rhs: Const16<u32>,
        offset: BranchOffset16,
    },
    BranchI64Eq {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI64EqImm16 {
        lhs: Reg,
        rhs: Const16<i64>,
        offset: BranchOffset16,
    },
    BranchI64Ne {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI64NeImm16 {
        lhs: Reg,
        rhs: Const16<i64>,
        offset: BranchOffset16,
    },
    BranchI64LtS {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI64LtSImm16Lhs {
        lhs: Const16<i64>,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI64LtSImm16Rhs {
        lhs: Reg,
        rhs: Const16<i64>,
        offset: BranchOffset16,
    },
    BranchI64LtU {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI64LtUImm16Lhs {
        lhs: Const16<u64>,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI64LtUImm16Rhs {
        lhs: Reg,
        rhs: Const16<u64>,
        offset: BranchOffset16,
    },
    BranchI64LeS {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI64LeSImm16Lhs {
        lhs: Const16<i64>,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI64LeSImm16Rhs {
        lhs: Reg,
        rhs: Const16<i64>,
        offset: BranchOffset16,
    },
    BranchI64LeU {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI64LeUImm16Lhs {
        lhs: Const16<u64>,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchI64LeUImm16Rhs {
        lhs: Reg,
        rhs: Const16<u64>,
        offset: BranchOffset16,
    },
    BranchF32Eq {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchF32Ne {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchF32Lt {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchF32Le {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchF64Eq {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchF64Ne {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchF64Lt {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchF64Le {
        lhs: Reg,
        rhs: Reg,
        offset: BranchOffset16,
    },
    BranchTable0 {
        index: Reg,
        len_targets: u32,
    },
    BranchTable1 {
        index: Reg,
        len_targets: u32,
    },
    BranchTable2 {
        index: Reg,
        len_targets: u32,
    },
    BranchTable3 {
        index: Reg,
        len_targets: u32,
    },
    BranchTableSpan {
        index: Reg,
        len_targets: u32,
    },
    BranchTableMany {
        index: Reg,
        len_targets: u32,
    },
    Copy {
        result: Reg,
        value: Reg,
    },
    Copy2 {
        results: FixedRegSpan<2>,
        values: [Reg; 2],
    },
    CopyImm32 {
        result: Reg,
        value: AnyConst32,
    },
    CopyI64Imm32 {
        result: Reg,
        value: Const32<i64>,
    },
    CopyF64Imm32 {
        result: Reg,
        value: Const32<f64>,
    },
    CopySpan {
        results: RegSpan,
        values: RegSpan,
        len: u16,
    },
    CopySpanNonOverlapping {
        results: RegSpan,
        values: RegSpan,
        len: u16,
    },
    CopyMany {
        results: RegSpan,
        values: [Reg; 2],
    },
    CopyManyNonOverlapping {
        results: RegSpan,
        values: [Reg; 2],
    },
    ReturnCallInternal0 {
        func: InternalFunc,
    },
    ReturnCallInternal {
        func: InternalFunc,
    },
    ReturnCallImported0 {
        func: Func,
    },
    ReturnCallImported {
        func: Func,
    },
    ReturnCallIndirect0 {
        func_type: FuncType,
    },
    ReturnCallIndirect0Imm16 {
        func_type: FuncType,
    },
    ReturnCallIndirect {
        func_type: FuncType,
    },
    ReturnCallIndirectImm16 {
        func_type: FuncType,
    },
    CallInternal0 {
        results: RegSpan,
        func: InternalFunc,
    },
    CallInternal {
        results: RegSpan,
        func: InternalFunc,
    },
    CallImported0 {
        results: RegSpan,
        func: Func,
    },
    CallImported {
        results: RegSpan,
        func: Func,
    },
    CallIndirect0 {
        results: RegSpan,
        func_type: FuncType,
    },
    CallIndirect0Imm16 {
        results: RegSpan,
        func_type: FuncType,
    },
    CallIndirect {
        results: RegSpan,
        func_type: FuncType,
    },
    CallIndirectImm16 {
        results: RegSpan,
        func_type: FuncType,
    },
    Select {
        result: Reg,
        lhs: Reg,
    },
    SelectImm32Rhs {
        result: Reg,
        lhs: Reg,
    },
    SelectImm32Lhs {
        result: Reg,
        lhs: AnyConst32,
    },
    SelectImm32 {
        result: Reg,
        lhs: AnyConst32,
    },
    SelectI64Imm32Rhs {
        result: Reg,
        lhs: Reg,
    },
    SelectI64Imm32Lhs {
        result: Reg,
        lhs: Const32<i64>,
    },
    SelectI64Imm32 {
        result: Reg,
        lhs: Const32<i64>,
    },
    SelectF64Imm32Rhs {
        result: Reg,
        lhs: Reg,
    },
    SelectF64Imm32Lhs {
        result: Reg,
        lhs: Const32<f64>,
    },
    SelectF64Imm32 {
        result: Reg,
        lhs: Const32<f64>,
    },
    RefFunc {
        result: Reg,
        func: Func,
    },
    GlobalGet {
        result: Reg,
        global: Global,
    },
    GlobalSet {
        input: Reg,
        global: Global,
    },
    GlobalSetI32Imm16 {
        input: Const16<i32>,
        global: Global,
    },
    GlobalSetI64Imm16 {
        input: Const16<i64>,
        global: Global,
    },
    Load32 {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    Load32At {
        result: Reg,
        address: Address32,
    },
    Load32Offset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    Load64 {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    Load64At {
        result: Reg,
        address: Address32,
    },
    Load64Offset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    I32Load8s {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    I32Load8sAt {
        result: Reg,
        address: Address32,
    },
    I32Load8sOffset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    I32Load8u {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    I32Load8uAt {
        result: Reg,
        address: Address32,
    },
    I32Load8uOffset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    I32Load16s {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    I32Load16sAt {
        result: Reg,
        address: Address32,
    },
    I32Load16sOffset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    I32Load16u {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    I32Load16uAt {
        result: Reg,
        address: Address32,
    },
    I32Load16uOffset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    I64Load8s {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    I64Load8sAt {
        result: Reg,
        address: Address32,
    },
    I64Load8sOffset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    I64Load8u {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    I64Load8uAt {
        result: Reg,
        address: Address32,
    },
    I64Load8uOffset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    I64Load16s {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    I64Load16sAt {
        result: Reg,
        address: Address32,
    },
    I64Load16sOffset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    I64Load16u {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    I64Load16uAt {
        result: Reg,
        address: Address32,
    },
    I64Load16uOffset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    I64Load32s {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    I64Load32sAt {
        result: Reg,
        address: Address32,
    },
    I64Load32sOffset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    I64Load32u {
        result: Reg,
        offset_lo: Offset64Lo,
    },
    I64Load32uAt {
        result: Reg,
        address: Address32,
    },
    I64Load32uOffset16 {
        result: Reg,
        ptr: Reg,
        offset: Offset16,
    },
    Store32 {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    Store32Offset16 {
        ptr: Reg,
        offset: Offset16,
        value: Reg,
    },
    Store32At {
        value: Reg,
        address: Address32,
    },
    Store64 {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    Store64Offset16 {
        ptr: Reg,
        offset: Offset16,
        value: Reg,
    },
    Store64At {
        value: Reg,
        address: Address32,
    },
    I32StoreImm16 {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I32StoreOffset16Imm16 {
        ptr: Reg,
        offset: Offset16,
        value: Const16<i32>,
    },
    I32StoreAtImm16 {
        value: Const16<i32>,
        address: Address32,
    },
    I32Store8 {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I32Store8Imm {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I32Store8Offset16 {
        ptr: Reg,
        offset: Offset16,
        value: Reg,
    },
    I32Store8Offset16Imm {
        ptr: Reg,
        offset: Offset16,
        value: i8,
    },
    I32Store8At {
        value: Reg,
        address: Address32,
    },
    I32Store8AtImm {
        value: i8,
        address: Address32,
    },
    I32Store16 {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I32Store16Imm {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I32Store16Offset16 {
        ptr: Reg,
        offset: Offset16,
        value: Reg,
    },
    I32Store16Offset16Imm {
        ptr: Reg,
        offset: Offset16,
        value: i16,
    },
    I32Store16At {
        value: Reg,
        address: Address32,
    },
    I32Store16AtImm {
        value: i16,
        address: Address32,
    },
    I64StoreImm16 {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I64StoreOffset16Imm16 {
        ptr: Reg,
        offset: Offset16,
        value: Const16<i64>,
    },
    I64StoreAtImm16 {
        value: Const16<i64>,
        address: Address32,
    },
    I64Store8 {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I64Store8Imm {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I64Store8Offset16 {
        ptr: Reg,
        offset: Offset16,
        value: Reg,
    },
    I64Store8Offset16Imm {
        ptr: Reg,
        offset: Offset16,
        value: i8,
    },
    I64Store8At {
        value: Reg,
        address: Address32,
    },
    I64Store8AtImm {
        value: i8,
        address: Address32,
    },
    I64Store16 {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I64Store16Imm {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I64Store16Offset16 {
        ptr: Reg,
        offset: Offset16,
        value: Reg,
    },
    I64Store16Offset16Imm {
        ptr: Reg,
        offset: Offset16,
        value: i16,
    },
    I64Store16At {
        value: Reg,
        address: Address32,
    },
    I64Store16AtImm {
        value: i16,
        address: Address32,
    },
    I64Store32 {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I64Store32Imm16 {
        ptr: Reg,
        offset_lo: Offset64Lo,
    },
    I64Store32Offset16 {
        ptr: Reg,
        offset: Offset16,
        value: Reg,
    },
    I64Store32Offset16Imm16 {
        ptr: Reg,
        offset: Offset16,
        value: Const16<i32>,
    },
    I64Store32At {
        value: Reg,
        address: Address32,
    },
    I64Store32AtImm16 {
        value: Const16<i32>,
        address: Address32,
    },
    I32Eq {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32EqImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32Ne {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32NeImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32LtS {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32LtSImm16Lhs {
        result: Reg,
        lhs: Const16<i32>,
        rhs: Reg,
    },
    I32LtSImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32LtU {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32LtUImm16Lhs {
        result: Reg,
        lhs: Const16<u32>,
        rhs: Reg,
    },
    I32LtUImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<u32>,
    },
    I32LeS {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32LeSImm16Lhs {
        result: Reg,
        lhs: Const16<i32>,
        rhs: Reg,
    },
    I32LeSImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32LeU {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32LeUImm16Lhs {
        result: Reg,
        lhs: Const16<u32>,
        rhs: Reg,
    },
    I32LeUImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<u32>,
    },
    I64Eq {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64EqImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i64>,
    },
    I64Ne {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64NeImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i64>,
    },
    I64LtS {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64LtSImm16Lhs {
        result: Reg,
        lhs: Const16<i64>,
        rhs: Reg,
    },
    I64LtSImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i64>,
    },
    I64LtU {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64LtUImm16Lhs {
        result: Reg,
        lhs: Const16<u64>,
        rhs: Reg,
    },
    I64LtUImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<u64>,
    },
    I64LeS {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64LeSImm16Lhs {
        result: Reg,
        lhs: Const16<i64>,
        rhs: Reg,
    },
    I64LeSImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i64>,
    },
    I64LeU {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64LeUImm16Lhs {
        result: Reg,
        lhs: Const16<u64>,
        rhs: Reg,
    },
    I64LeUImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<u64>,
    },
    F32Eq {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F32Ne {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F32Lt {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F32Le {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F64Eq {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F64Ne {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F64Lt {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F64Le {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32Clz {
        result: Reg,
        input: Reg,
    },
    I32Ctz {
        result: Reg,
        input: Reg,
    },
    I32Popcnt {
        result: Reg,
        input: Reg,
    },
    I32Add {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32AddImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32Sub {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32SubImm16Lhs {
        result: Reg,
        lhs: Const16<i32>,
        rhs: Reg,
    },
    I32Mul {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32MulImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32DivS {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32DivSImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<NonZeroI32>,
    },
    I32DivSImm16Lhs {
        result: Reg,
        lhs: Const16<i32>,
        rhs: Reg,
    },
    I32DivU {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32DivUImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<NonZeroU32>,
    },
    I32DivUImm16Lhs {
        result: Reg,
        lhs: Const16<u32>,
        rhs: Reg,
    },
    I32RemS {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32RemSImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<NonZeroI32>,
    },
    I32RemSImm16Lhs {
        result: Reg,
        lhs: Const16<i32>,
        rhs: Reg,
    },
    I32RemU {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32RemUImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<NonZeroU32>,
    },
    I32RemUImm16Lhs {
        result: Reg,
        lhs: Const16<u32>,
        rhs: Reg,
    },
    I32And {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32AndEqz {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32AndEqzImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32AndImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32Or {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32OrEqz {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32OrEqzImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32OrImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32Xor {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32XorEqz {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32XorEqzImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32XorImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i32>,
    },
    I32Shl {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32ShlBy {
        result: Reg,
        lhs: Reg,
        rhs: ShiftAmount<i32>,
    },
    I32ShlImm16 {
        result: Reg,
        lhs: Const16<i32>,
        rhs: Reg,
    },
    I32ShrU {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32ShrUBy {
        result: Reg,
        lhs: Reg,
        rhs: ShiftAmount<i32>,
    },
    I32ShrUImm16 {
        result: Reg,
        lhs: Const16<i32>,
        rhs: Reg,
    },
    I32ShrS {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32ShrSBy {
        result: Reg,
        lhs: Reg,
        rhs: ShiftAmount<i32>,
    },
    I32ShrSImm16 {
        result: Reg,
        lhs: Const16<i32>,
        rhs: Reg,
    },
    I32Rotl {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32RotlBy {
        result: Reg,
        lhs: Reg,
        rhs: ShiftAmount<i32>,
    },
    I32RotlImm16 {
        result: Reg,
        lhs: Const16<i32>,
        rhs: Reg,
    },
    I32Rotr {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I32RotrBy {
        result: Reg,
        lhs: Reg,
        rhs: ShiftAmount<i32>,
    },
    I32RotrImm16 {
        result: Reg,
        lhs: Const16<i32>,
        rhs: Reg,
    },
    I64Clz {
        result: Reg,
        input: Reg,
    },
    I64Ctz {
        result: Reg,
        input: Reg,
    },
    I64Popcnt {
        result: Reg,
        input: Reg,
    },
    I64Add {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64AddImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i64>,
    },
    I64Sub {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64SubImm16Lhs {
        result: Reg,
        lhs: Const16<i64>,
        rhs: Reg,
    },
    I64Mul {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64MulImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i64>,
    },
    I64DivS {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64DivSImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<NonZeroI64>,
    },
    I64DivSImm16Lhs {
        result: Reg,
        lhs: Const16<i64>,
        rhs: Reg,
    },
    I64DivU {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64DivUImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<NonZeroU64>,
    },
    I64DivUImm16Lhs {
        result: Reg,
        lhs: Const16<u64>,
        rhs: Reg,
    },
    I64RemS {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64RemSImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<NonZeroI64>,
    },
    I64RemSImm16Lhs {
        result: Reg,
        lhs: Const16<i64>,
        rhs: Reg,
    },
    I64RemU {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64RemUImm16Rhs {
        result: Reg,
        lhs: Reg,
        rhs: Const16<NonZeroU64>,
    },
    I64RemUImm16Lhs {
        result: Reg,
        lhs: Const16<u64>,
        rhs: Reg,
    },
    I64And {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64AndImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i64>,
    },
    I64Or {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64OrImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i64>,
    },
    I64Xor {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64XorImm16 {
        result: Reg,
        lhs: Reg,
        rhs: Const16<i64>,
    },
    I64Shl {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64ShlBy {
        result: Reg,
        lhs: Reg,
        rhs: ShiftAmount<i64>,
    },
    I64ShlImm16 {
        result: Reg,
        lhs: Const16<i64>,
        rhs: Reg,
    },
    I64ShrU {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64ShrUBy {
        result: Reg,
        lhs: Reg,
        rhs: ShiftAmount<i64>,
    },
    I64ShrUImm16 {
        result: Reg,
        lhs: Const16<i64>,
        rhs: Reg,
    },
    I64ShrS {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64ShrSBy {
        result: Reg,
        lhs: Reg,
        rhs: ShiftAmount<i64>,
    },
    I64ShrSImm16 {
        result: Reg,
        lhs: Const16<i64>,
        rhs: Reg,
    },
    I64Rotl {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64RotlBy {
        result: Reg,
        lhs: Reg,
        rhs: ShiftAmount<i64>,
    },
    I64RotlImm16 {
        result: Reg,
        lhs: Const16<i64>,
        rhs: Reg,
    },
    I64Rotr {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    I64RotrBy {
        result: Reg,
        lhs: Reg,
        rhs: ShiftAmount<i64>,
    },
    I64RotrImm16 {
        result: Reg,
        lhs: Const16<i64>,
        rhs: Reg,
    },
    I32WrapI64 {
        result: Reg,
        input: Reg,
    },
    I32Extend8S {
        result: Reg,
        input: Reg,
    },
    I32Extend16S {
        result: Reg,
        input: Reg,
    },
    I64Extend8S {
        result: Reg,
        input: Reg,
    },
    I64Extend16S {
        result: Reg,
        input: Reg,
    },
    I64Extend32S {
        result: Reg,
        input: Reg,
    },
    F32Abs {
        result: Reg,
        input: Reg,
    },
    F32Neg {
        result: Reg,
        input: Reg,
    },
    F32Ceil {
        result: Reg,
        input: Reg,
    },
    F32Floor {
        result: Reg,
        input: Reg,
    },
    F32Trunc {
        result: Reg,
        input: Reg,
    },
    F32Nearest {
        result: Reg,
        input: Reg,
    },
    F32Sqrt {
        result: Reg,
        input: Reg,
    },
    F32Add {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F32Sub {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F32Mul {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F32Div {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F32Min {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F32Max {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F32Copysign {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F32CopysignImm {
        result: Reg,
        lhs: Reg,
        rhs: Sign<f32>,
    },
    F64Abs {
        result: Reg,
        input: Reg,
    },
    F64Neg {
        result: Reg,
        input: Reg,
    },
    F64Ceil {
        result: Reg,
        input: Reg,
    },
    F64Floor {
        result: Reg,
        input: Reg,
    },
    F64Trunc {
        result: Reg,
        input: Reg,
    },
    F64Nearest {
        result: Reg,
        input: Reg,
    },
    F64Sqrt {
        result: Reg,
        input: Reg,
    },
    F64Add {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F64Sub {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F64Mul {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F64Div {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F64Min {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F64Max {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F64Copysign {
        result: Reg,
        lhs: Reg,
        rhs: Reg,
    },
    F64CopysignImm {
        result: Reg,
        lhs: Reg,
        rhs: Sign<f64>,
    },
    I32TruncF32S {
        result: Reg,
        input: Reg,
    },
    I32TruncF32U {
        result: Reg,
        input: Reg,
    },
    I32TruncF64S {
        result: Reg,
        input: Reg,
    },
    I32TruncF64U {
        result: Reg,
        input: Reg,
    },
    I64TruncF32S {
        result: Reg,
        input: Reg,
    },
    I64TruncF32U {
        result: Reg,
        input: Reg,
    },
    I64TruncF64S {
        result: Reg,
        input: Reg,
    },
    I64TruncF64U {
        result: Reg,
        input: Reg,
    },
    I32TruncSatF32S {
        result: Reg,
        input: Reg,
    },
    I32TruncSatF32U {
        result: Reg,
        input: Reg,
    },
    I32TruncSatF64S {
        result: Reg,
        input: Reg,
    },
    I32TruncSatF64U {
        result: Reg,
        input: Reg,
    },
    I64TruncSatF32S {
        result: Reg,
        input: Reg,
    },
    I64TruncSatF32U {
        result: Reg,
        input: Reg,
    },
    I64TruncSatF64S {
        result: Reg,
        input: Reg,
    },
    I64TruncSatF64U {
        result: Reg,
        input: Reg,
    },
    F32DemoteF64 {
        result: Reg,
        input: Reg,
    },
    F64PromoteF32 {
        result: Reg,
        input: Reg,
    },
    F32ConvertI32S {
        result: Reg,
        input: Reg,
    },
    F32ConvertI32U {
        result: Reg,
        input: Reg,
    },
    F32ConvertI64S {
        result: Reg,
        input: Reg,
    },
    F32ConvertI64U {
        result: Reg,
        input: Reg,
    },
    F64ConvertI32S {
        result: Reg,
        input: Reg,
    },
    F64ConvertI32U {
        result: Reg,
        input: Reg,
    },
    F64ConvertI64S {
        result: Reg,
        input: Reg,
    },
    F64ConvertI64U {
        result: Reg,
        input: Reg,
    },
    TableGet {
        result: Reg,
        index: Reg,
    },
    TableGetImm {
        result: Reg,
        index: Const32<u64>,
    },
    TableSize {
        result: Reg,
        table: Table,
    },
    TableSet {
        index: Reg,
        value: Reg,
    },
    TableSetAt {
        value: Reg,
        index: Const32<u64>,
    },
    TableCopy {
        dst: Reg,
        src: Reg,
        len: Reg,
    },
    TableCopyTo {
        dst: Const16<u64>,
        src: Reg,
        len: Reg,
    },
    TableCopyFrom {
        dst: Reg,
        src: Const16<u64>,
        len: Reg,
    },
    TableCopyFromTo {
        dst: Const16<u64>,
        src: Const16<u64>,
        len: Reg,
    },
    TableCopyExact {
        dst: Reg,
        src: Reg,
        len: Const16<u64>,
    },
    TableCopyToExact {
        dst: Const16<u64>,
        src: Reg,
        len: Const16<u64>,
    },
    TableCopyFromExact {
        dst: Reg,
        src: Const16<u64>,
        len: Const16<u64>,
    },
    TableCopyFromToExact {
        dst: Const16<u64>,
        src: Const16<u64>,
        len: Const16<u64>,
    },
    TableInit {
        dst: Reg,
        src: Reg,
        len: Reg,
    },
    TableInitTo {
        dst: Const16<u64>,
        src: Reg,
        len: Reg,
    },
    TableInitFrom {
        dst: Reg,
        src: Const16<u32>,
        len: Reg,
    },
    TableInitFromTo {
        dst: Const16<u64>,
        src: Const16<u32>,
        len: Reg,
    },
    TableInitExact {
        dst: Reg,
        src: Reg,
        len: Const16<u32>,
    },
    TableInitToExact {
        dst: Const16<u64>,
        src: Reg,
        len: Const16<u32>,
    },
    TableInitFromExact {
        dst: Reg,
        src: Const16<u32>,
        len: Const16<u32>,
    },
    TableInitFromToExact {
        dst: Const16<u64>,
        src: Const16<u32>,
        len: Const16<u32>,
    },
    TableFill {
        dst: Reg,
        len: Reg,
        value: Reg,
    },
    TableFillAt {
        dst: Const16<u64>,
        len: Reg,
        value: Reg,
    },
    TableFillExact {
        dst: Reg,
        len: Const16<u64>,
        value: Reg,
    },
    TableFillAtExact {
        dst: Const16<u64>,
        len: Const16<u64>,
        value: Reg,
    },
    TableGrow {
        result: Reg,
        delta: Reg,
        value: Reg,
    },
    TableGrowImm {
        result: Reg,
        delta: Const16<u64>,
        value: Reg,
    },
    ElemDrop {
        index: Elem,
    },
    DataDrop {
        index: Data,
    },
    MemorySize {
        result: Reg,
        memory: Memory,
    },
    MemoryGrow {
        result: Reg,
        delta: Reg,
    },
    MemoryGrowBy {
        result: Reg,
        delta: u32,
    },
    MemoryCopy {
        dst: Reg,
        src: Reg,
        len: Reg,
    },
    MemoryCopyTo {
        dst: Const16<u64>,
        src: Reg,
        len: Reg,
    },
    MemoryCopyFrom {
        dst: Reg,
        src: Const16<u64>,
        len: Reg,
    },
    MemoryCopyFromTo {
        dst: Const16<u64>,
        src: Const16<u64>,
        len: Reg,
    },
    MemoryCopyExact {
        dst: Reg,
        src: Reg,
        len: Const16<u64>,
    },
    MemoryCopyToExact {
        dst: Const16<u64>,
        src: Reg,
        len: Const16<u64>,
    },
    MemoryCopyFromExact {
        dst: Reg,
        src: Const16<u64>,
        len: Const16<u64>,
    },
    MemoryCopyFromToExact {
        dst: Const16<u64>,
        src: Const16<u64>,
        len: Const16<u64>,
    },
    MemoryFill {
        dst: Reg,
        value: Reg,
        len: Reg,
    },
    MemoryFillAt {
        dst: Const16<u64>,
        value: Reg,
        len: Reg,
    },
    MemoryFillImm {
        dst: Reg,
        value: u8,
        len: Reg,
    },
    MemoryFillExact {
        dst: Reg,
        value: Reg,
        len: Const16<u64>,
    },
    MemoryFillAtImm {
        dst: Const16<u64>,
        value: u8,
        len: Reg,
    },
    MemoryFillAtExact {
        dst: Const16<u64>,
        value: Reg,
        len: Const16<u64>,
    },
    MemoryFillImmExact {
        dst: Reg,
        value: u8,
        len: Const16<u64>,
    },
    MemoryFillAtImmExact {
        dst: Const16<u64>,
        value: u8,
        len: Const16<u64>,
    },
    MemoryInit {
        dst: Reg,
        src: Reg,
        len: Reg,
    },
    MemoryInitTo {
        dst: Const16<u64>,
        src: Reg,
        len: Reg,
    },
    MemoryInitFrom {
        dst: Reg,
        src: Const16<u32>,
        len: Reg,
    },
    MemoryInitFromTo {
        dst: Const16<u64>,
        src: Const16<u32>,
        len: Reg,
    },
    MemoryInitExact {
        dst: Reg,
        src: Reg,
        len: Const16<u32>,
    },
    MemoryInitToExact {
        dst: Const16<u64>,
        src: Reg,
        len: Const16<u32>,
    },
    MemoryInitFromExact {
        dst: Reg,
        src: Const16<u32>,
        len: Const16<u32>,
    },
    MemoryInitFromToExact {
        dst: Const16<u64>,
        src: Const16<u32>,
        len: Const16<u32>,
    },
    TableIndex {
        index: Table,
    },
    MemoryIndex {
        index: Memory,
    },
    DataIndex {
        index: Data,
    },
    ElemIndex {
        index: Elem,
    },
    Const32 {
        value: AnyConst32,
    },
    I64Const32 {
        value: Const32<i64>,
    },
    F64Const32 {
        value: Const32<f64>,
    },
    BranchTableTarget {
        results: RegSpan,
        offset: BranchOffset,
    },
    BranchTableTargetNonOverlapping {
        results: RegSpan,
        offset: BranchOffset,
    },
    Imm16AndImm32 {
        imm16: AnyConst16,
        imm32: AnyConst32,
    },
    RegisterAndImm32 {
        reg: Reg,
        imm: AnyConst32,
    },
    RegisterSpan {
        span: BoundedRegSpan,
    },
    Register {
        reg: Reg,
    },
    Register2 {
        regs: [Reg; 2],
    },
    Register3 {
        regs: [Reg; 3],
    },
    RegisterList {
        regs: [Reg; 3],
    },
    CallIndirectParams {
        index: Reg,
        table: Table,
    },
    CallIndirectParamsImm16 {
        index: Const16<u64>,
        table: Table,
    },
}

A Wasmi instruction.

Wasmi instructions are composed of so-called instruction words. This type represents all such words and for simplicity we call the type Instruction, still.

Most instructions are composed of a single instruction word. An example of this is Instruction::I32Add. However, some instructions, like Instruction::Select, are composed of two or more instruction words.

The Wasmi bytecode translation makes sure that instructions always appear in valid sequences. The Wasmi executor relies on the guarantees that the Wasmi translator provides.

The documentation of each Instruction describes its encoding in the #Encoding section of its documentation if it requires more than a single instruction for its encoding.

Variants

Trap

Traps the execution with the given TrapCode.

Note

Used to represent Wasm unreachable instruction as well as code paths that are determined to always lead to traps during execution. For example division by constant zero.

Fields

trap_code: TrapCode

ConsumeFuel

Instruction generated to consume fuel for its associated basic block.

Note

These instructions are only generated if fuel metering is enabled.

Fields

block_fuel: BlockFuel

Return

A Wasm return instruction.

Note

Returns nothing.

ReturnReg

A Wasm return instruction.

Note

Returns a single value stored in a register.

Fields

value: Reg

The returned value.

ReturnReg2

A Wasm return instruction.

Note

Returns two values stored in registers.

Fields

values: [Reg; 2]

The returned values.

ReturnReg3

A Wasm return instruction.

Note

Returns three values stored in registers.

Fields

values: [Reg; 3]

The returned values.

ReturnImm32

A Wasm return instruction.

Note

Returns a single 32-bit constant value.

Fields

value: AnyConst32

The returned 32-bit constant value.

ReturnI64Imm32

A Wasm return instruction.

Note

Returns a single 32-bit encoded i64 constant value.

Fields

value: Const32<i64>

The returned constant value.

ReturnF64Imm32

A Wasm return instruction.

Note

Returns a single 32-bit encoded f64 constant value.

Fields

value: Const32<f64>

The returned constant value.

ReturnSpan

A Wasm return instruction.

Note

Returns values as stored in the bounded RegSpan.

Fields

values: BoundedRegSpan

The RegSpan that represents the registers that store the returned values.

ReturnMany

A Wasm return instruction.

Note

Returns many values accessed by registers.

Encoding

Must be followed by

1. Zero or more Instruction::RegisterList
2. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

values: [Reg; 3]

The first three returned values.

ReturnNez

A conditional return instruction.

Note

This is used to translate certain conditional Wasm branches such as br_if. Returns back to the caller if and only if the condition value is non zero.

Fields

condition: Reg

The register holding the condition to evaluate against zero.

ReturnNezReg

A conditional return instruction.

Note

Variant of Instruction::ReturnNez returning a single Reg value if the condition evaluates to true.

Fields

condition: Reg

The register holding the condition to evaluate against zero.

value: Reg

The returned value.

ReturnNezReg2

A conditional return instruction.

Note

Variant of Instruction::ReturnNez returning two Reg value if the condition evaluates to true.

Fields

condition: Reg

The register holding the condition to evaluate against zero.

values: [Reg; 2]

The returned value.

ReturnNezImm32

A conditional return instruction.

Note

Variant of Instruction::ReturnNez returning a single AnyConst32 value if the condition evaluates to true.

Fields

condition: Reg

The register holding the condition to evaluate against zero.

value: AnyConst32

The returned value.

ReturnNezI64Imm32

A conditional return instruction.

Note

Variant of Instruction::ReturnNez returning a single 32-bit encoded i64 value if the condition evaluates to true.

Fields

condition: Reg

The register holding the condition to evaluate against zero.

value: Const32<i64>

The returned value.

ReturnNezF64Imm32

A conditional return instruction.

Note

Variant of Instruction::ReturnNez returning a single 32-bit encoded f64 value if the condition evaluates to true.

Fields

condition: Reg

The register holding the condition to evaluate against zero.

value: Const32<f64>

The returned value.

ReturnNezSpan

A conditional return instruction.

Note

Variant of Instruction::ReturnNez returning two or more values.

Fields

condition: Reg

The register holding the condition to evaluate against zero.

values: BoundedRegSpan

The returned values.

ReturnNezMany

A conditional return instruction.

Note

Variant of Instruction::ReturnNez returning multiple register values.

Encoding

Must be followed by

1. Zero or more Instruction::RegisterList
2. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

condition: Reg

The register holding the condition to evaluate against zero.

values: [Reg; 2]

The first returned value.

Branch

A Wasm br instruction.

Fields

offset: BranchOffset

The branching offset for the instruction pointer.

BranchCmpFallback

A fallback instruction for cmp+branch instructions with branch offsets that cannot be 16-bit encoded.

Note

This instruction fits in a single instruction word but arguably executes slower than cmp+branch instructions with a 16-bit encoded branch offset. It only ever gets encoded and used whenever a branch offset of a cmp+branch instruction cannot be 16-bit encoded.

Fields

lhs: Reg

The left-hand side value for the comparison.

rhs: Reg

The right-hand side value for the comparison.

Note

We allocate constant values as function local constant values and use their register to only require a single fallback instruction variant.

params: Reg

The register that stores the ComparatorAndOffset of this instruction.

Note

The ComparatorAndOffset is loaded from register as u64 value and decoded into a ComparatorAndOffset before access its comparator and 32-bit branch offset fields.

BranchI32And

A fused i32.and and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32AndImm16

A fused i32.and and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32Or

A fused i32.or and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32OrImm16

A fused i32.or and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32Xor

A fused i32.xor and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32XorImm16

A fused i32.xor and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32AndEqz

A fused i32.eqz(i32.and) and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32AndEqzImm16

A fused i32.eqz(i32.and) and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32OrEqz

A fused i32.eqz(i32.or) and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32OrEqzImm16

A fused i32.eqz(i32.or) and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32XorEqz

A fused i32.eqz(i32.xor) and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32XorEqzImm16

A fused i32.eqz(i32.xor) and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32Eq

A fused i32.eq and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32EqImm16

A fused i32.eq and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32Ne

A fused i32.ne and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32NeImm16

A fused i32.ne and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LtS

A fused i32.lt_s and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LtSImm16Lhs

A fused i32.lt_s and branch instruction with 16-bit immediate lhs value.

Fields

lhs: Const16<i32>

The right-hand side operand to the conditional operator.

rhs: Reg

The left-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LtSImm16Rhs

A fused i32.lt_s and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LtU

A fused i32.lt_u and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LtUImm16Lhs

A fused i32.lt_u and branch instruction with 16-bit immediate lhs value.

Fields

lhs: Const16<u32>

The right-hand side operand to the conditional operator.

rhs: Reg

The left-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LtUImm16Rhs

A fused i32.lt_u and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<u32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LeS

A fused i32.le_s and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LeSImm16Lhs

A fused i32.le_s and branch instruction with 16-bit immediate lhs value.

Fields

lhs: Const16<i32>

The right-hand side operand to the conditional operator.

rhs: Reg

The left-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LeSImm16Rhs

A fused i32.le_s and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LeU

A fused i32.le_u and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LeUImm16Lhs

A fused i32.le_u and branch instruction with 16-bit immediate lhs value.

Fields

lhs: Const16<u32>

The right-hand side operand to the conditional operator.

rhs: Reg

The left-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI32LeUImm16Rhs

A fused i32.le_u and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<u32>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64Eq

A fused i64.eq and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64EqImm16

A fused i64.eq and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i64>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64Ne

A fused i64.ne and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64NeImm16

A fused i64.ne and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i64>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LtS

A fused i64.lt_s and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LtSImm16Lhs

A fused i64.lt_s and branch instruction with 16-bit immediate lhs value.

Fields

lhs: Const16<i64>

The right-hand side operand to the conditional operator.

rhs: Reg

The left-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LtSImm16Rhs

A fused i64.lt_s and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i64>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LtU

A fused i64.lt_u and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LtUImm16Lhs

A fused i64.lt_u and branch instruction with 16-bit immediate lhs value.

Fields

lhs: Const16<u64>

The right-hand side operand to the conditional operator.

rhs: Reg

The left-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LtUImm16Rhs

A fused i64.lt_u and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<u64>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LeS

A fused i64.le_s and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LeSImm16Lhs

A fused i64.le_s and branch instruction with 16-bit immediate lhs value.

Fields

lhs: Const16<i64>

The right-hand side operand to the conditional operator.

rhs: Reg

The left-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LeSImm16Rhs

A fused i64.le_s and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<i64>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LeU

A fused i64.le_u and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LeUImm16Lhs

A fused i64.le_u and branch instruction with 16-bit immediate lhs value.

Fields

lhs: Const16<u64>

The right-hand side operand to the conditional operator.

rhs: Reg

The left-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchI64LeUImm16Rhs

A fused i64.le_u and branch instruction with 16-bit immediate rhs value.

Fields

lhs: Reg

The left-hand side operand to the conditional operator.

rhs: Const16<u64>

The right-hand side operand to the conditional operator.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchF32Eq

A fused f32.eq and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchF32Ne

A fused f32.ne and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchF32Lt

A fused f32.lt and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchF32Le

A fused f32.le and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchF64Eq

A fused f64.eq and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchF64Ne

A fused f64.ne and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchF64Lt

A fused f64.lt and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchF64Le

A fused f64.le and branch instruction.

Fields

lhs: Reg

The left-hand side operand to the branch conditional.

rhs: Reg

The right-hand side operand to the branch conditional.

offset: BranchOffset16

The 16-bit encoded branch offset.

BranchTable0

A Wasm br_table equivalent Wasmi instruction.

Encoding

Followed len_target times by

• Instruction::Branch
• Instruction::Return

Fields

index: Reg

The register holding the index of the instruction.

len_targets: u32

The number of branch table targets including the default target.

BranchTable1

A Wasm br_table equivalent Wasmi instruction.

Encoding

1. Followed by one of

• Instruction::Register
• Instruction::Const32
• Instruction::I64Const32
• Instruction::F64Const32

2. Followed len_target times by

• Instruction::BranchTableTarget
• Instruction::ReturnReg
• Instruction::ReturnImm32
• Instruction::ReturnI64Imm32
• Instruction::ReturnF64Imm32

Fields

index: Reg

The register holding the index of the instruction.

len_targets: u32

The number of branch table targets including the default target.

BranchTable2

A Wasm br_table equivalent Wasmi instruction.

Encoding

1. Followed by Instruction::Register2.
2. Followed len_target times by

• Instruction::BranchTableTarget
• Instruction::ReturnReg2

Fields

index: Reg

The register holding the index of the instruction.

len_targets: u32

The number of branch table targets including the default target.

BranchTable3

A Wasm br_table equivalent Wasmi instruction.

Encoding

1. Followed by Instruction::Register3.
2. Followed len_target times by

• Instruction::BranchTableTarget
• Instruction::ReturnReg3

Fields

index: Reg

The register holding the index of the instruction.

len_targets: u32

The number of branch table targets including the default target.

BranchTableSpan

A Wasm br_table equivalent Wasmi instruction.

Note

All branch table targets must share the same destination registers.

Encoding

1. Followed by one of Instruction::RegisterSpan.
2. Followed len_target times by

• Instruction::BranchTableTarget
• Instruction::BranchTableTargetNonOverlapping
• Instruction::ReturnSpan

Fields

index: Reg

The register holding the index of the instruction.

len_targets: u32

The number of branch table targets including the default target.

BranchTableMany

A Wasm br_table equivalent Wasmi instruction.

Note

All branch table targets must share the same destination registers.

Encoding

1. Followed by Instruction::RegisterList encoding.
2. Followed len_target times by

• Instruction::BranchTableTarget
• Instruction::BranchTableTargetNonOverlapping
• Instruction::Return

Fields

index: Reg

The register holding the index of the instruction.

len_targets: u32

The number of branch table targets including the default target.

Copy

Copies value to result.

Note

This is a Wasmi utility instruction used to translate Wasm control flow.

Fields

result: Reg

The register(s) storing the result of the instruction.

value: Reg

The register holding the value to copy.

Copy2

Copies two Reg values to results.

Note

This is a Wasmi utility instruction used to translate Wasm control flow.

Fields

results: FixedRegSpan<2>

The register(s) storing the result of the instruction.

values: [Reg; 2]

The registers holding the values to copy.

CopyImm32

Copies the 32-bit immediate value to result.

Note

Variant of Instruction::Copy for 32-bit encoded immediate values. Read Instruction::Copy for more information about this instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

value: AnyConst32

The 32-bit encoded immediate value to copy.

CopyI64Imm32

Copies the 32-bit encoded i64 immediate value to result.

Note

• Variant of Instruction::Copy for 32-bit encodable i64 immediate values.
• Upon execution the 32-bit encoded i32 value is sign extended to i64 and copied into result.
• Read Instruction::Copy for more information about this instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

value: Const32<i64>

The 32-bit encoded i64 immediate value to copy.

CopyF64Imm32

Copies the 32-bit encoded f64 immediate value to result.

Note

• Variant of Instruction::Copy for 32-bit encodable f64 immediate values.
• Upon execution the 32-bit encoded f32 value is promoted to f64 and copied into result.
• Read Instruction::Copy for more information about this instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

value: Const32<f64>

The 32-bit encoded i64 immediate value to copy.

CopySpan

Copies len contiguous values RegSpan into results RegSpan.

Copies registers: registers[results..results+len] <- registers[values..values+len]

Note

This Instruction serves as an optimization for cases were it is possible to copy whole spans instead of many individual register values bit by bit.

Fields

results: RegSpan

The register(s) storing the result of the instruction.

values: RegSpan

The contiguous registers holding the inputs of this instruction.

len: u16

The amount of copied registers.

CopySpanNonOverlapping

Variant of Instruction::CopySpan that assumes that results and values span do not overlap.

Fields

results: RegSpan

The register(s) storing the result of the instruction.

values: RegSpan

The contiguous registers holding the inputs of this instruction.

len: u16

The amount of copied registers.

CopyMany

Copies some Reg values into results RegSpan.

Encoding

Must be followed by

1. Zero or more Instruction::RegisterList
2. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

results: RegSpan

The register(s) storing the result of the instruction.

values: [Reg; 2]

The first two input registers to copy.

CopyManyNonOverlapping

Variant of Instruction::CopyMany that assumes that results and values do not overlap.

Must be followed by

1. Zero or more Instruction::RegisterList
2. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

results: RegSpan

The register(s) storing the result of the instruction.

values: [Reg; 2]

The first two input registers to copy.

ReturnCallInternal0

Wasm return_call equivalent Wasmi instruction.

Note

Used for tail calling internally compiled Wasm functions without parameters.

Fields

func: InternalFunc

The called internal function.

ReturnCallInternal

Wasm return_call equivalent Wasmi instruction.

Note

Used for tail calling internally compiled Wasm functions with parameters.

Encoding (Parameters)

Must be followed by

1. Zero or more Instruction::RegisterList
2. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

func: InternalFunc

The called internal function.

ReturnCallImported0

Wasm return_call equivalent Wasmi instruction.

Note

Used for tail calling imported Wasm functions without parameters.

Fields

func: Func

The called imported function.

ReturnCallImported

Wasm return_call equivalent Wasmi instruction.

Note

Used for tail calling imported Wasm functions with parameters.

Encoding (Parameters)

Must be followed by

1. Zero or more Instruction::RegisterList
2. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

func: Func

The called imported function.

ReturnCallIndirect0

Wasm return_call_indirect equivalent Wasmi instruction.

Note

Used for indirectly calling Wasm functions without parameters.

Encoding

Must be followed by Instruction::CallIndirectParams encoding table and index.

Fields

func_type: FuncType

The called internal function.

ReturnCallIndirect0Imm16

Wasm return_call_indirect equivalent Wasmi instruction with 16-bit immediate index.

Note

Used for indirectly calling Wasm functions without parameters.

Encoding

Must be followed by Instruction::CallIndirectParamsImm16 encoding table and index.

Fields

func_type: FuncType

The called internal function.

ReturnCallIndirect

Wasm return_call_indirect equivalent Wasmi instruction.

Note

Used for indirectly calling Wasm functions with parameters.

Encoding

Must be followed by

1. Instruction::CallIndirectParams: encoding table and index
2. Zero or more Instruction::RegisterList
3. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

func_type: FuncType

The called internal function.

ReturnCallIndirectImm16

Wasm return_call_indirect equivalent Wasmi instruction with 16-bit immediate index.

Note

Used for indirectly calling Wasm functions with parameters.

Encoding

Must be followed by

1. Instruction::CallIndirectParamsImm16: encoding table and index
2. Zero or more Instruction::RegisterList
3. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

func_type: FuncType

The called internal function.

CallInternal0

Wasm call equivalent Wasmi instruction.

Note

Used for calling internally compiled Wasm functions without parameters.

Fields

results: RegSpan

The register(s) storing the result of the instruction.

func: InternalFunc

The called internal function.

CallInternal

Wasm call equivalent Wasmi instruction.

Note

Used for calling internally compiled Wasm functions with parameters.

Encoding (Parameters)

Must be followed by

1. Zero or more Instruction::RegisterList
2. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

results: RegSpan

The register(s) storing the result of the instruction.

func: InternalFunc

The called internal function.

CallImported0

Wasm call equivalent Wasmi instruction.

Note

Used for calling imported Wasm functions without parameters.

Fields

results: RegSpan

The register(s) storing the result of the instruction.

func: Func

The called imported function.

CallImported

Wasm call equivalent Wasmi instruction.

Note

Used for calling imported Wasm functions with parameters.

Encoding (Parameters)

Must be followed by

1. Zero or more Instruction::RegisterList
2. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

results: RegSpan

The register(s) storing the result of the instruction.

func: Func

The called imported function.

CallIndirect0

Wasm call_indirect equivalent Wasmi instruction.

Note

Used for indirectly calling Wasm functions without parameters.

Encoding

Must be followed by Instruction::CallIndirectParams encoding table and index.

Fields

results: RegSpan

The register(s) storing the result of the instruction.

func_type: FuncType

The called internal function.

CallIndirect0Imm16

Wasm call_indirect equivalent Wasmi instruction with 16-bit immediate inde value.

Note

Used for indirectly calling Wasm functions without parameters.

Encoding

Must be followed by Instruction::CallIndirectParamsImm16 encoding table and index.

Fields

results: RegSpan

The register(s) storing the result of the instruction.

func_type: FuncType

The called internal function.

CallIndirect

Wasm call_indirect equivalent Wasmi instruction.

Note

Used for indirectly calling Wasm functions with parameters.

Encoding

Must be followed by

1. Instruction::CallIndirectParams: encoding table and index
2. Zero or more Instruction::RegisterList
3. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

results: RegSpan

The register(s) storing the result of the instruction.

func_type: FuncType

The called internal function.

CallIndirectImm16

Wasm call_indirect equivalent Wasmi instruction with 16-bit immediate index value.

Note

Used for indirectly calling Wasm functions with parameters.

Encoding

Must be followed by

1. Instruction::CallIndirectParamsImm16: encoding table and index
2. Zero or more Instruction::RegisterList
3. Followed by one of
   • Instruction::Register
   • Instruction::Register2
   • Instruction::Register3

Fields

results: RegSpan

The register(s) storing the result of the instruction.

func_type: FuncType

The called internal function.

Select

A Wasm select equivalent Wasmi instruction.

Encoding

Must be followed by Instruction::Register2 to encode condition and rhs.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

SelectImm32Rhs

A Wasm select equivalent Wasmi instruction with 32-bit immediate rhs value.

Encoding

Must be followed by Instruction::RegisterAndImm32 to encode condition and rhs.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

SelectImm32Lhs

A Wasm select equivalent Wasmi instruction with 32-bit immediate lhs value.

Encoding

Must be followed by Instruction::Register2 to encode condition and lhs.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: AnyConst32

The register holding the left-hand side value.

SelectImm32

A Wasm select equivalent Wasmi instruction with 32-bit immediate lhs and rhs values.

Encoding

Must be followed by Instruction::RegisterAndImm32 to encode condition and rhs.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: AnyConst32

The register holding the left-hand side value.

SelectI64Imm32Rhs

A Wasm select equivalent Wasmi instruction with 32-bit encoded i64 immediate lhs value.

Encoding

Must be followed by Instruction::RegisterAndImm32 to encode condition and rhs.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

SelectI64Imm32Lhs

A Wasm select equivalent Wasmi instruction with 32-bit encoded i64 immediate lhs value.

Encoding

Must be followed by Instruction::Register2 to encode condition and rhs.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const32<i64>

The register holding the left-hand side value.

SelectI64Imm32

A Wasm select equivalent Wasmi instruction with 32-bit encoded i64 immediate lhs and rhs values.

Encoding

Must be followed by Instruction::RegisterAndImm32 to encode condition and rhs.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const32<i64>

The register holding the left-hand side value.

SelectF64Imm32Rhs

A Wasm select equivalent Wasmi instruction with 32-bit encoded f64 immediate rhs value.

Encoding

Must be followed by Instruction::RegisterAndImm32 to encode condition and rhs.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

SelectF64Imm32Lhs

A Wasm select equivalent Wasmi instruction with 32-bit encoded f64 immediate lhs value.

Encoding

Must be followed by Instruction::Register2 to encode condition and rhs.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const32<f64>

The register holding the left-hand side value.

SelectF64Imm32

A Wasm select equivalent Wasmi instruction with 32-bit encoded f64 immediate lhs and rhs value.

Encoding

Must be followed by Instruction::RegisterAndImm32 to encode condition and rhs.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const32<f64>

The register holding the left-hand side value.

RefFunc

A Wasm ref.func equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

func: Func

The index of the referenced function.

GlobalGet

Wasm global.get equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

global: Global

The index identifying the global variable for the global.get instruction.

GlobalSet

Wasm global.set equivalent Wasmi instruction.

Fields

input: Reg

The register holding the value to be stored in the global variable.

global: Global

The index identifying the global variable for the global.set instruction.

GlobalSetI32Imm16

Wasm global.set equivalent Wasmi instruction.

Note

Variant of Instruction::GlobalSet for 16-bit encoded i32 immutable input values.

Fields

input: Const16<i32>

The 16-bit encoded i32 value.

global: Global

The index identifying the global variable for the global.set instruction.

GlobalSetI64Imm16

Wasm global.set equivalent Wasmi instruction.

Note

Variant of Instruction::GlobalSet for 16-bit encoded i64 immutable input values.

Fields

input: Const16<i64>

The 16-bit encoded i64 value.

global: Global

The index identifying the global variable for the global.set instruction.

Load32

Load instruction for 32-bit values.

Note

Equivalent to Wasm {i32,f32}.load instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

Load32At

Load instruction for 32-bit values and a 32-bit encoded address.

Note

Variant of Instruction::Load32 with a constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

Load32Offset16

Load instruction for 32-bit values.

Note

• Variant of Instruction::Load32 with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

Load64

Load instruction for 64-bit values.

Note

Equivalent to Wasm {i64,f64}.load instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

Load64At

Load instruction for 64-bit values and a 32-bit encoded address.

Note

Variant of Instruction::Load32 with a constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

Load64Offset16

Load instruction for 64-bit values.

Note

• Variant of Instruction::Load64 with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

I32Load8s

Wasm i32.load8_s equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I32Load8sAt

Wasm i32.load8_s equivalent Wasmi instruction.

Note

Variant of Instruction::I32Load8s with a 32-bit constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

I32Load8sOffset16

Wasm i32.load8_s equivalent Wasmi instruction.

Note

• Variant of Instruction::I32Load8s with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

I32Load8u

Wasm i32.load8_u equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I32Load8uAt

Wasm i32.load8_u equivalent Wasmi instruction.

Note

Variant of Instruction::I32Load8u with a 32-bit constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

I32Load8uOffset16

Wasm i32.load8_u equivalent Wasmi instruction.

Note

• Variant of Instruction::I32Load8u with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

I32Load16s

Wasm i32.load16_s equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I32Load16sAt

Wasm i32.load16_s equivalent Wasmi instruction.

Note

Variant of Instruction::I32Load16s with a 32-bit constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

I32Load16sOffset16

Wasm i32.load16_s equivalent Wasmi instruction.

Note

• Variant of Instruction::I32Load16s with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

I32Load16u

Wasm i32.load16_u equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I32Load16uAt

Wasm i32.load16_u equivalent Wasmi instruction.

Note

Variant of Instruction::I32Load16u with a 32-bit constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

I32Load16uOffset16

Wasm i32.load16_u equivalent Wasmi instruction.

Note

• Variant of Instruction::I32Load16u with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

I64Load8s

Wasm i64.load8_s equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Load8sAt

Wasm i64.load8_s equivalent Wasmi instruction.

Note

Variant of Instruction::I64Load8s with a 32-bit constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

I64Load8sOffset16

Wasm i64.load8_s equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Load8s with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

I64Load8u

Wasm i64.load8_u equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Load8uAt

Wasm i64.load8_u equivalent Wasmi instruction.

Note

Variant of Instruction::I64Load8u with a 32-bit constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

I64Load8uOffset16

Wasm i64.load8_u equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Load8u with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

I64Load16s

Wasm i64.load16_s equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Load16sAt

Wasm i64.load16_s equivalent Wasmi instruction.

Note

Variant of Instruction::I64Load16s with a 32-bit constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

I64Load16sOffset16

Wasm i64.load16_s equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Load16s with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

I64Load16u

Wasm i64.load16_u equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Load16uAt

Wasm i64.load16_u equivalent Wasmi instruction.

Note

Variant of Instruction::I64Load16u with a 32-bit constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

I64Load16uOffset16

Wasm i64.load16_u equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Load16u with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

I64Load32s

Wasm i64.load32_s equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Load32sAt

Wasm i64.load32_s equivalent Wasmi instruction.

Note

Variant of Instruction::I64Load32s with a 32-bit constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

I64Load32sOffset16

Wasm i64.load32_s equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Load32s with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

I64Load32u

Wasm i64.load32_u equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding ptr and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

result: Reg

The register(s) storing the result of the instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Load32uAt

Wasm i64.load32_u equivalent Wasmi instruction.

Note

Variant of Instruction::I64Load32u with a 32-bit constant load address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

result: Reg

The register(s) storing the result of the instruction.

address: Address32

The ptr+offset address of the load instruction.

I64Load32uOffset16

Wasm i64.load32_u equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Load32u with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

ptr: Reg

The register storing the pointer of the load instruction.

offset: Offset16

The 16-bit encoded offset of the load instruction.

Store32

Store instruction for 32-bit values.

Note

Equivalent to Wasm {i32,f32}.store instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

Store32Offset16

Store instruction for 32-bit values.

Note

• Variant of Instruction::Store32 with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: Reg

The value to be stored.

Store32At

Store instruction for 32-bit values.

Note

Variant of Instruction::Store32 with an immediate ptr+offset address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: Reg

The value to be stored.

address: Address32

The constant address to store the value.

Store64

Store instruction for 64-bit values.

Note

Equivalent to Wasm {i64,f64}.store instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

Store64Offset16

Store instruction for 64-bit values.

Note

• Variant of Instruction::Store64 with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: Reg

The value to be stored.

Store64At

Store instruction for 64-bit values.

Note

Variant of Instruction::Store64 with an immediate ptr+offset address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: Reg

The value to be stored.

address: Address32

The constant address to store the value.

I32StoreImm16

Wasm i32.store equivalent Wasmi instruction.

Note

Variant of Instruction::Store32 with 16-bit immediate value.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I32StoreOffset16Imm16

Wasm i32.store equivalent Wasmi instruction.

Note

• Variant of Instruction::Store32Offset16 with 16-bit immediate value.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: Const16<i32>

The value to be stored.

I32StoreAtImm16

Wasm i32.store equivalent Wasmi instruction.

Note

Variant of Instruction::Store32At with 16-bit immediate value.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: Const16<i32>

The value to be stored.

address: Address32

The constant address to store the value.

I32Store8

Wasm i32.store equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I32Store8Imm

Wasm i32.store8 equivalent Wasmi instruction.

Note

Variant of Instruction::I32Store8 with immediate value.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I32Store8Offset16

Wasm i32.store8 equivalent Wasmi instruction.

Note

• Variant of Instruction::I32Store8 with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: Reg

The value to be stored.

I32Store8Offset16Imm

Wasm i32.store8 equivalent Wasmi instruction.

Note

• Variant of Instruction::I32Store8Offset16 with immediate value.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: i8

The value to be stored.

I32Store8At

Wasm i32.store8 equivalent Wasmi instruction.

Note

Variant of Instruction::I32Store8 with an immediate ptr+offset address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: Reg

The value to be stored.

address: Address32

The constant address to store the value.

I32Store8AtImm

Wasm i32.store8 equivalent Wasmi instruction.

Note

Variant of Instruction::I32Store8At with immediate value.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: i8

The value to be stored.

address: Address32

The constant address to store the value.

I32Store16

Wasm i32.store16 equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I32Store16Imm

Wasm i32.store16 equivalent Wasmi instruction.

Note

Variant of Instruction::I32Store16 with immediate value.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I32Store16Offset16

Wasm i32.store16 equivalent Wasmi instruction.

Note

• Variant of Instruction::I32Store16 with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: Reg

The value to be stored.

I32Store16Offset16Imm

Wasm i32.store16 equivalent Wasmi instruction.

Note

• Variant of Instruction::I32Store16Offset16 with immediate value.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: i16

The value to be stored.

I32Store16At

Wasm i32.store16 equivalent Wasmi instruction.

Note

Variant of Instruction::I32Store16 with an immediate ptr+offset address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: Reg

The value to be stored.

address: Address32

The constant address to store the value.

I32Store16AtImm

Wasm i32.store16 equivalent Wasmi instruction.

Note

Variant of Instruction::I32Store16At with immediate value.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: i16

The value to be stored.

address: Address32

The constant address to store the value.

I64StoreImm16

Wasm i64.store equivalent Wasmi instruction.

Note

Variant of Instruction::Store64 with 16-bit immediate value.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64StoreOffset16Imm16

Wasm i64.store equivalent Wasmi instruction.

Note

• Variant of Instruction::Store64Offset16 with 16-bit immediate value.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: Const16<i64>

The value to be stored.

I64StoreAtImm16

Wasm i64.store equivalent Wasmi instruction.

Note

Variant of Instruction::Store64At with 16-bit immediate value.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: Const16<i64>

The value to be stored.

address: Address32

The constant address to store the value.

I64Store8

Wasm i64.store8 equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Store8Imm

Wasm i64.store8 equivalent Wasmi instruction.

Note

Variant of Instruction::I64Store8 with immediate value.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Store8Offset16

Wasm i64.store8 equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Store8 with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: Reg

The value to be stored.

I64Store8Offset16Imm

Wasm i64.store8 equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Store8Offset16 with immediate value.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: i8

The value to be stored.

I64Store8At

Wasm i64.store8 equivalent Wasmi instruction.

Note

Variant of Instruction::I64Store8 with an immediate ptr+offset address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: Reg

The value to be stored.

address: Address32

The constant address to store the value.

I64Store8AtImm

Wasm i64.store8 equivalent Wasmi instruction.

Note

Variant of Instruction::I64Store8At with immediate value.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: i8

The value to be stored.

address: Address32

The constant address to store the value.

I64Store16

Wasm i64.store16 equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Store16Imm

Wasm i64.store16 equivalent Wasmi instruction.

Note

Variant of Instruction::I64Store16 with immediate value.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Store16Offset16

Wasm i64.store16 equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Store16 with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: Reg

The value to be stored.

I64Store16Offset16Imm

Wasm i64.store16 equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Store16Offset16 with immediate value.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: i16

The value to be stored.

I64Store16At

Wasm i64.store16 equivalent Wasmi instruction.

Note

Variant of Instruction::I64Store16 with an immediate ptr+offset address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: Reg

The value to be stored.

address: Address32

The constant address to store the value.

I64Store16AtImm

Wasm i64.store16 equivalent Wasmi instruction.

Note

Variant of Instruction::I64Store16At with immediate value.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: i16

The value to be stored.

address: Address32

The constant address to store the value.

I64Store32

Wasm i64.store32 equivalent Wasmi instruction.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Store32Imm16

Wasm i64.store32 equivalent Wasmi instruction.

Note

Variant of Instruction::I64Store32 with 16-bit immediate value.

Encoding

Followed by

1. Instruction::RegisterAndImm32: encoding value and offset_hi
2. Optional Instruction::MemoryIndex: encoding memory index used

If Instruction::MemoryIndex is missing the default memory is used.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset_lo: Offset64Lo

The lower 32-bit of the 64-bit load offset.

I64Store32Offset16

Wasm i64.store32 equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Store32 with a 16-bit offset.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: Reg

The value to be stored.

I64Store32Offset16Imm16

Wasm i64.store32 equivalent Wasmi instruction.

Note

• Variant of Instruction::I64Store32Offset16 with 16-bit immediate value.
• Operates on the default Wasm memory instance.

Fields

ptr: Reg

The register storing the pointer of the store instruction.

offset: Offset16

The register storing the pointer offset of the store instruction.

value: Const16<i32>

The value to be stored.

I64Store32At

Wasm i64.store32 equivalent Wasmi instruction.

Note

Variant of Instruction::I64Store32 with an immediate ptr+offset address.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: Reg

The value to be stored.

address: Address32

The constant address to store the value.

I64Store32AtImm16

Wasm i64.store32 equivalent Wasmi instruction.

Note

Variant of Instruction::I64Store32At with 16-bit immediate value.

Encoding

Optionally followed by an Instruction::MemoryIndex encoding memory.

• Operates on the default Wasm memory instance if missing.

Fields

value: Const16<i32>

The value to be stored.

address: Address32

The constant address to store the value.

I32Eq

Wasm i32.eq equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32EqImm16

Wasm i32.eq equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32Ne

Wasm i32.ne equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32NeImm16

Wasm i32.ne equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32LtS

Wasm i32.lt_s equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32LtSImm16Lhs

Wasm i32.lt_s equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32LtSImm16Rhs

Wasm i32.lt_s equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32LtU

Wasm i32.lt_u equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32LtUImm16Lhs

Wasm i32.lt_u equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<u32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32LtUImm16Rhs

Wasm i32.lt_u equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<u32>

The 16-bit immediate value.

I32LeS

Wasm i32.le_s equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32LeSImm16Lhs

Wasm i32.le_s equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32LeSImm16Rhs

Wasm i32.le_s equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32LeU

Wasm i32.le_u equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32LeUImm16Lhs

Wasm i32.le_u equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<u32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32LeUImm16Rhs

Wasm i32.le_u equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<u32>

The 16-bit immediate value.

I64Eq

Wasm i64.eq equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64EqImm16

Wasm i64.eq equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i64>

The 16-bit immediate value.

I64Ne

Wasm i64.ne equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64NeImm16

Wasm i64.ne equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i64>

The 16-bit immediate value.

I64LtS

Wasm i64.lt_s equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64LtSImm16Lhs

Wasm i64.lt_s equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64LtSImm16Rhs

Wasm i64.lt_s equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i64>

The 16-bit immediate value.

I64LtU

Wasm i64.lt_u equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64LtUImm16Lhs

Wasm i64.lt_u equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<u64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64LtUImm16Rhs

Wasm i64.lt_u equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<u64>

The 16-bit immediate value.

I64LeS

Wasm i64.le_s equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64LeSImm16Lhs

Wasm i64.le_s equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64LeSImm16Rhs

Wasm i64.le_s equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i64>

The 16-bit immediate value.

I64LeU

Wasm i64.le_u equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64LeUImm16Lhs

Wasm i64.le_u equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<u64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64LeUImm16Rhs

Wasm i64.le_u equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<u64>

The 16-bit immediate value.

F32Eq

Wasm f32.eq equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F32Ne

Wasm f32.ne equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F32Lt

Wasm f32.lt equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F32Le

Wasm f32.le equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F64Eq

Wasm f64.eq equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F64Ne

Wasm f64.ne equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F64Lt

Wasm f64.lt equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F64Le

Wasm f64.le equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32Clz

i32 count-leading-zeros (clz) instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32Ctz

i32 count-trailing-zeros (ctz) instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32Popcnt

i32 pop-count instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32Add

i32 add instruction: r0 = r1 + r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32AddImm16

i32 add (small) immediate instruction: r0 = r1 + c0

Note

Optimized variant of Instruction::I32Add for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32Sub

i32 subtract instruction: r0 = r1 - r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32SubImm16Lhs

i32 subtract immediate instruction: r0 = c0 - r1

Note

• Optimized variant of Instruction::I32Sub for 16-bit constant values.
• Required instruction since subtraction is not commutative.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32Mul

i32 multiply instruction: r0 = r1 * r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32MulImm16

i32 multiply immediate instruction: r0 = r1 * c0

Note

Optimized variant of Instruction::I32Mul for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32DivS

i32 signed-division instruction: r0 = r1 / r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32DivSImm16Rhs

i32 signed-division immediate instruction: r0 = r1 / c0

Note

• Optimized variant of Instruction::I32DivS for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<NonZeroI32>

The 16-bit immediate value.

I32DivSImm16Lhs

i32 signed-division immediate instruction: r0 = c0 / r1

Note

• Optimized variant of Instruction::I32DivU for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.
• Required instruction since signed-division is not commutative.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32DivU

i32 unsigned-division instruction: r0 = r1 / r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32DivUImm16Rhs

i32 unsigned-division immediate instruction: r0 = r1 / c0

Note

Guarantees that the right-hand side operand is not zero.

Encoding

Optimized variant of Instruction::I32DivU for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<NonZeroU32>

The 16-bit immediate value.

I32DivUImm16Lhs

i32 unsigned-division immediate instruction: r0 = c0 / r1

Note

• Optimized variant of Instruction::I32DivU for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.
• Required instruction since i32 unsigned-division is not commutative.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<u32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32RemS

i32 signed-remainder instruction: r0 = r1 % r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32RemSImm16Rhs

i32 signed-remainder immediate instruction: r0 = r1 % c0

Note

• Optimized variant of Instruction::I32RemS for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<NonZeroI32>

The 16-bit immediate value.

I32RemSImm16Lhs

i32 signed-remainder immediate instruction: r0 = c0 % r1

Note

• Optimized variant of Instruction::I32RemS for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.
• Required instruction since i32 signed-remainder is not commutative.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32RemU

i32 unsigned-remainder instruction: r0 = r1 % r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32RemUImm16Rhs

i32 signed-remainder immediate instruction: r0 = r1 % c0

Note

• Optimized variant of Instruction::I32RemU for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<NonZeroU32>

The 16-bit immediate value.

I32RemUImm16Lhs

i32 unsigned-remainder immediate instruction: r0 = c0 % r1

Note

• Optimized variant of Instruction::I32RemU for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.
• Required instruction since unsigned-remainder is not commutative.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<u32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32And

i32 bitwise-and instruction: r0 = r1 & r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32AndEqz

Fused Wasm i32.and + i32.eqz Instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32AndEqzImm16

Fused Wasm i32.and + i32.eqz Instruction with 16-bit encoded immediate.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32AndImm16

i32 bitwise-and (small) immediate instruction: r0 = r1 & c0

Note

Optimized variant of Instruction::I32And for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32Or

i32 bitwise-or instruction: r0 = r1 & r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32OrEqz

Fused Wasm i32.or + i32.eqz Instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32OrEqzImm16

Fused Wasm i32.or + i32.eqz Instruction with 16-bit encoded immediate.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32OrImm16

i32 bitwise-or (small) immediate instruction: r0 = r1 & c0

Note

Optimized variant of Instruction::I32Or for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32Xor

i32 bitwise-or instruction: r0 = r1 ^ r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32XorEqz

Fused Wasm i32.xor + i32.eqz Instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32XorEqzImm16

Fused Wasm i32.xor + i32.eqz Instruction with 16-bit encoded immediate.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32XorImm16

i32 bitwise-or (small) immediate instruction: r0 = r1 ^ c0

Note

Optimized variant of Instruction::I32Xor for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i32>

The 16-bit immediate value.

I32Shl

A Wasm i32.shl equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32ShlBy

A Wasm i32.shl equivalent Wasmi instruction with 16-bit immediate rhs operand.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: ShiftAmount<i32>

The 16-bit immediate value.

I32ShlImm16

A Wasm i32.shl equivalent Wasmi instruction with 16-bit immediate lhs operand.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32ShrU

A Wasm i32.shr_u equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32ShrUBy

A Wasm i32.shr_u equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: ShiftAmount<i32>

The 16-bit immediate value.

I32ShrUImm16

A Wasm i32.shr_u equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32ShrS

A Wasm i32.shr_s equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32ShrSBy

A Wasm i32.shr_s equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: ShiftAmount<i32>

The 16-bit immediate value.

I32ShrSImm16

A Wasm i32.shr_s equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32Rotl

A Wasm i32.rotl equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32RotlBy

A Wasm i32.rotl equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: ShiftAmount<i32>

The 16-bit immediate value.

I32RotlImm16

A Wasm i32.rotl equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32Rotr

A Wasm i32.rotr equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I32RotrBy

A Wasm i32.rotr equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: ShiftAmount<i32>

The 16-bit immediate value.

I32RotrImm16

A Wasm i32.rotr equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i32>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64Clz

i64 count-leading-zeros (clz) instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64Ctz

i64 count-trailing-zeros (ctz) instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64Popcnt

i64 pop-count instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64Add

i64 add instruction: r0 = r1 + r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64AddImm16

i64 add (small) immediate instruction: r0 = r1 + c0

Note

Optimized variant of Instruction::I64Add for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i64>

The 16-bit immediate value.

I64Sub

i64 subtract instruction: r0 = r1 - r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64SubImm16Lhs

i64 subtract immediate instruction: r0 = c0 - r1

Note

• Optimized variant of Instruction::I64Sub for 16-bit constant values.
• Required instruction since subtraction is not commutative.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64Mul

i64 multiply instruction: r0 = r1 * r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64MulImm16

i64 multiply immediate instruction: r0 = r1 * c0

Note

Optimized variant of Instruction::I64Mul for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i64>

The 16-bit immediate value.

I64DivS

i64 signed-division instruction: r0 = r1 / r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64DivSImm16Rhs

i64 signed-division immediate instruction: r0 = r1 / c0

Note

• Optimized variant of Instruction::I64DivS for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<NonZeroI64>

The 16-bit immediate value.

I64DivSImm16Lhs

i32 signed-division immediate instruction: r0 = c0 / r1

Note

• Guarantees that the right-hand side operand is not zero.
• Required instruction since signed-division is not commutative.
• Optimized variant of Instruction::I64DivU for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64DivU

i64 unsigned-division instruction: r0 = r1 / r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64DivUImm16Rhs

i64 unsigned-division immediate instruction: r0 = r1 / c0

Note

Guarantees that the right-hand side operand is not zero.

Encoding

Optimized variant of Instruction::I64DivU for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<NonZeroU64>

The 16-bit immediate value.

I64DivUImm16Lhs

i64 unsigned-division immediate instruction: r0 = c0 / r1

Note

• Optimized variant of Instruction::I64DivU for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.
• Required instruction since unsigned-division is not commutative.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<u64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64RemS

i64 signed-remainder instruction: r0 = r1 % r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64RemSImm16Rhs

i64 signed-remainder immediate instruction: r0 = r1 % c0

Note

• Optimized variant of Instruction::I64RemS for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<NonZeroI64>

The 16-bit immediate value.

I64RemSImm16Lhs

i64 signed-remainder immediate instruction: r0 = c0 % r1

Note

• Optimized variant of Instruction::I64RemS for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.
• Required instruction since signed-remainder is not commutative.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64RemU

i64 unsigned-remainder instruction: r0 = r1 % r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64RemUImm16Rhs

i64 signed-remainder immediate instruction: r0 = r1 % c0

Note

• Optimized variant of Instruction::I64RemU for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<NonZeroU64>

The 16-bit immediate value.

I64RemUImm16Lhs

i64 unsigned-remainder immediate instruction: r0 = c0 % r1

Note

• Optimized variant of Instruction::I64RemU for 16-bit constant values.
• Guarantees that the right-hand side operand is not zero.
• Required instruction since unsigned-remainder is not commutative.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<u64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64And

i64 bitwise-and instruction: r0 = r1 & r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64AndImm16

i64 bitwise-and (small) immediate instruction: r0 = r1 & c0

Note

Optimized variant of Instruction::I64And for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i64>

The 16-bit immediate value.

I64Or

i64 bitwise-or instruction: r0 = r1 & r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64OrImm16

i64 bitwise-or (small) immediate instruction: r0 = r1 & c0

Note

Optimized variant of Instruction::I64Or for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i64>

The 16-bit immediate value.

I64Xor

i64 bitwise-or instruction: r0 = r1 ^ r2

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64XorImm16

i64 bitwise-or (small) immediate instruction: r0 = r1 ^ c0

Note

Optimized variant of Instruction::I64Xor for 16-bit constant values.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: Const16<i64>

The 16-bit immediate value.

I64Shl

A Wasm i64.shl equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64ShlBy

A Wasm i64.shl equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: ShiftAmount<i64>

The 16-bit immediate value.

I64ShlImm16

A Wasm i64.shl equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64ShrU

A Wasm i64.shr_u equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64ShrUBy

A Wasm i64.shr_u equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: ShiftAmount<i64>

The 16-bit immediate value.

I64ShrUImm16

A Wasm i64.shr_u equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64ShrS

A Wasm i64.shr_s equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64ShrSBy

A Wasm i64.shr_s equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: ShiftAmount<i64>

The 16-bit immediate value.

I64ShrSImm16

A Wasm i64.shr_s equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64Rotl

A Wasm i64.rotl equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64RotlBy

A Wasm i64.rotl equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: ShiftAmount<i64>

The 16-bit immediate value.

I64RotlImm16

A Wasm i64.rotl equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I64Rotr

A Wasm i64.rotr equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

I64RotrBy

A Wasm i64.rotr equivalent Wasmi instruction with 16-bit immediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding one of the operands.

rhs: ShiftAmount<i64>

The 16-bit immediate value.

I64RotrImm16

A Wasm i64.rotr equivalent Wasmi instruction with 16-bit immediate lhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Const16<i64>

The 16-bit immediate value.

rhs: Reg

The register holding one of the operands.

I32WrapI64

Wasm i32.wrap_i64 instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32Extend8S

Wasm i32.extend8_s instruction.

Note

Instruction from the Wasm sign-extension proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32Extend16S

Wasm i32.extend16_s instruction.

Note

Instruction from the Wasm sign-extension proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64Extend8S

Wasm i64.extend8_s instruction.

Note

Instruction from the Wasm sign-extension proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64Extend16S

Wasm(UnaryInstr) i64.extend16_s instruction.

Note

Instruction from the Wasm sign-extension proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64Extend32S

Wasm i64.extend32_s instruction.

Note

Instruction from the Wasm sign-extension proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32Abs

Wasm f32.abs equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32Neg

Wasm f32.neg equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32Ceil

Wasm f32.ceil equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32Floor

Wasm f32.floor equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32Trunc

Wasm f32.trunc equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32Nearest

Wasm f32.nearest equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32Sqrt

Wasm f32.sqrt equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32Add

Wasm f32.add equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F32Sub

Wasm f32.sub equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F32Mul

Wasm f32.mul equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F32Div

Wasm f32.div equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F32Min

Wasm f32.min equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F32Max

Wasm f32.max equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F32Copysign

Wasm f32.copysign equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F32CopysignImm

Wasm f32.copysign equivalent Wasmi instruction with NaN canonicalization.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Sign<f32>

The register holding the right-hand side value.

F64Abs

Wasm f64.abs equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64Neg

Wasm f64.neg equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64Ceil

Wasm f64.ceil equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64Floor

Wasm f64.floor equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64Trunc

Wasm f64.trunc equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64Nearest

Wasm f64.nearest equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64Sqrt

Wasm f64.sqrt equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64Add

Wasm f64.add equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F64Sub

Wasm f64.sub equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F64Mul

Wasm f64.mul equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F64Div

Wasm f64.div equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F64Min

Wasm f64.min equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F64Max

Wasm f64.max equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F64Copysign

Wasm f64.copysign equivalent Wasmi instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Reg

The register holding the right-hand side value.

F64CopysignImm

Wasm f64.copysign equivalent Wasmi instruction with imediate rhs value.

Fields

result: Reg

The register(s) storing the result of the instruction.

lhs: Reg

The register holding the left-hand side value.

rhs: Sign<f64>

The register holding the right-hand side value.

I32TruncF32S

Wasm i32.trunc_f32_s instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32TruncF32U

Wasm i32.trunc_f32_u instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32TruncF64S

Wasm i32.trunc_f64_s instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32TruncF64U

Wasm i32.trunc_f64_u instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64TruncF32S

Wasm i64.trunc_f32_s instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64TruncF32U

Wasm i64.trunc_f32_u instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64TruncF64S

Wasm i64.trunc_f64_s instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64TruncF64U

Wasm i64.trunc_f64_u instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32TruncSatF32S

Wasm i32.trunc_sat_f32_s instruction.

Note

Instruction from the Wasm non-trapping float-to-int conversions proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32TruncSatF32U

Wasm i32.trunc_sat_f32_u instruction.

Note

Instruction from the Wasm non-trapping float-to-int conversions proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32TruncSatF64S

Wasm i32.trunc_sat_f64_s instruction.

Note

Instruction from the Wasm non-trapping float-to-int conversions proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I32TruncSatF64U

Wasm i32.trunc_sat_f64_u instruction.

Note

Instruction from the Wasm non-trapping float-to-int conversions proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64TruncSatF32S

Wasm i64.trunc_sat_f32_s instruction.

Note

Instruction from the Wasm non-trapping float-to-int conversions proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64TruncSatF32U

Wasm i64.trunc_sat_f32_u instruction.

Note

Instruction from the Wasm non-trapping float-to-int conversions proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64TruncSatF64S

Wasm i64.trunc_sat_f64_s instruction.

Note

Instruction from the Wasm non-trapping float-to-int conversions proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

I64TruncSatF64U

Wasm i64.trunc_sat_f64_u instruction.

Note

Instruction from the Wasm non-trapping float-to-int conversions proposal.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32DemoteF64

Wasm f32.demote_f64 instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64PromoteF32

Wasm f64.promote_f32 instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32ConvertI32S

Wasm f32.convert_i32_s instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32ConvertI32U

Wasm f32.convert_i32_u instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32ConvertI64S

Wasm f32.convert_i64_s instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F32ConvertI64U

Wasm f32.convert_i64_u instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64ConvertI32S

Wasm f64.convert_i32_s instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64ConvertI32U

Wasm f64.convert_i32_u instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64ConvertI64S

Wasm f64.convert_i64_s instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

F64ConvertI64U

Wasm f64.convert_i64_u instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

input: Reg

The register holding the input of the instruction.

TableGet

A Wasm table.get instruction: result = table[index]

Encoding

This Instruction must be followed by an Instruction::TableIndex.

Fields

result: Reg

The register(s) storing the result of the instruction.

index: Reg

The register storing the index of the table element to get.

TableGetImm

Variant of Instruction::TableGet with constant index value.

Encoding

This Instruction must be followed by an Instruction::TableIndex.

Fields

result: Reg

The register(s) storing the result of the instruction.

index: Const32<u64>

The constant index value of the table element to get.

TableSize

A Wasm table.size instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

table: Table

The index identifying the table for the instruction.

TableSet

A Wasm table.set instruction: table[index] = value

Encoding

This Instruction must be followed by an Instruction::TableIndex.

Fields

index: Reg

The register holding the index of the instruction.

value: Reg

The register holding the value of the instruction.

TableSetAt

Variant of Instruction::TableSet with constant index value.

Encoding

This Instruction must be followed by an Instruction::TableIndex.

Fields

value: Reg

The register holding the value of the instruction.

index: Const32<u64>

The constant index of the instruction.

TableCopy

Wasm table.copy <dst> <src> instruction.

Copies elements from table<src>[src..src+len] to table<dst>[dst..dst+len].

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the dst Wasm table instance
2. Instruction::TableIndex: the src Wasm table instance

Fields

dst: Reg

The start index of the dst table.

src: Reg

The start index of the src table.

len: Reg

The number of copied elements.

TableCopyTo

Variant of Instruction::TableCopy with a constant 16-bit dst index.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the dst Wasm table instance
2. Instruction::TableIndex: the src Wasm table instance

Fields

dst: Const16<u64>

The start index of the dst table.

src: Reg

The start index of the src table.

len: Reg

The number of copied elements.

TableCopyFrom

Variant of Instruction::TableCopy with a constant 16-bit src index.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the dst Wasm table instance
2. Instruction::TableIndex: the src Wasm table instance

Fields

dst: Reg

The start index of the dst table.

src: Const16<u64>

The start index of the src table.

len: Reg

The number of copied elements.

TableCopyFromTo

Variant of Instruction::TableCopy with a constant 16-bit dst and src indices.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the dst Wasm table instance
2. Instruction::TableIndex: the src Wasm table instance

Fields

dst: Const16<u64>

The start index of the dst table.

src: Const16<u64>

The start index of the src table.

len: Reg

The number of copied elements.

TableCopyExact

Variant of Instruction::TableCopy with a constant 16-bit len field.

Note

This instruction copies exactly len elements between the tables.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the dst Wasm table instance
2. Instruction::TableIndex: the src Wasm table instance

Fields

dst: Reg

The start index of the dst table.

src: Reg

The start index of the src table.

len: Const16<u64>

The number of copied elements.

TableCopyToExact

Variant of Instruction::TableCopy with a constant 16-bit len and dst.

Note

This instruction copies exactly len elements between the tables.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the dst Wasm table instance
2. Instruction::TableIndex: the src Wasm table instance

Fields

dst: Const16<u64>

The start index of the dst table.

src: Reg

The start index of the src table.

len: Const16<u64>

The number of copied elements.

TableCopyFromExact

Variant of Instruction::TableCopy with a constant 16-bit len and src.

Note

This instruction copies exactly len elements between the tables.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the dst Wasm table instance
2. Instruction::TableIndex: the src Wasm table instance

Fields

dst: Reg

The start index of the dst table.

src: Const16<u64>

The start index of the src table.

len: Const16<u64>

The number of copied elements.

TableCopyFromToExact

Variant of Instruction::TableCopy with a constant 16-bit len and src.

Note

This instruction copies exactly len elements between the tables.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the dst Wasm table instance
2. Instruction::TableIndex: the src Wasm table instance

Fields

dst: Const16<u64>

The start index of the dst table.

src: Const16<u64>

The start index of the src table.

len: Const16<u64>

The number of copied elements.

TableInit

Wasm table.init <table> <elem> instruction.

Copies elements from table[src..src+len] to table[dst..dst+len].

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the Wasm table instance
2. Instruction::ElemIndex: the Wasm element segment instance

Fields

dst: Reg

The start index of the dst table.

src: Reg

The start index of the src table.

len: Reg

The number of copied elements.

TableInitTo

Variant of Instruction::TableInit with a constant 16-bit dst index.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the Wasm table instance
2. Instruction::ElemIndex: the Wasm element segment instance

Fields

dst: Const16<u64>

The start index of the dst table.

src: Reg

The start index of the src table.

len: Reg

The number of copied elements.

TableInitFrom

Variant of Instruction::TableInit with a constant 16-bit src index.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the Wasm table instance
2. Instruction::ElemIndex: the Wasm element segment instance

Fields

dst: Reg

The start index of the dst table.

src: Const16<u32>

The start index of the src table.

len: Reg

The number of copied elements.

TableInitFromTo

Variant of Instruction::TableInit with a constant 16-bit dst and src indices.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the Wasm table instance
2. Instruction::ElemIndex: the Wasm element segment instance

Fields

dst: Const16<u64>

The start index of the dst table.

src: Const16<u32>

The start index of the src table.

len: Reg

The number of copied elements.

TableInitExact

Variant of Instruction::TableInit with a constant 16-bit len field.

Note

This instruction copies exactly len elements between the tables.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the Wasm table instance
2. Instruction::ElemIndex: the Wasm element segment instance

Fields

dst: Reg

The start index of the dst table.

src: Reg

The start index of the src table.

len: Const16<u32>

The number of copied elements.

TableInitToExact

Variant of Instruction::TableInit with a constant 16-bit len and dst.

Note

This instruction copies exactly len elements between the tables.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the Wasm table instance
2. Instruction::ElemIndex: the Wasm element segment instance

Fields

dst: Const16<u64>

The start index of the dst table.

src: Reg

The start index of the src table.

len: Const16<u32>

The number of copied elements.

TableInitFromExact

Variant of Instruction::TableInit with a constant 16-bit len and src.

Note

This instruction copies exactly len elements between the tables.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the Wasm table instance
2. Instruction::ElemIndex: the Wasm element segment instance

Fields

dst: Reg

The start index of the dst table.

src: Const16<u32>

The start index of the src table.

len: Const16<u32>

The number of copied elements.

TableInitFromToExact

Variant of Instruction::TableInit with a constant 16-bit len and src.

Note

This instruction copies exactly len elements between the tables.

Encoding

This Instruction must be followed by

1. Instruction::TableIndex: the Wasm table instance
2. Instruction::ElemIndex: the Wasm element segment instance

Fields

dst: Const16<u64>

The start index of the dst table.

src: Const16<u32>

The start index of the src table.

len: Const16<u32>

The number of copied elements.

TableFill

Wasm table.fill <table> instruction: table[dst..dst+len] = value

Encoding

Followed by Instruction::TableIndex encoding the Wasm table instance.

Fields

dst: Reg

The start index of the table to fill.

len: Reg

The number of elements to fill.

value: Reg

The value of the filled elements.

TableFillAt

Variant of Instruction::TableFill with 16-bit constant dst index.

Encoding

Followed by Instruction::TableIndex encoding the Wasm table instance.

Fields

dst: Const16<u64>

The start index of the table to fill.

len: Reg

The number of elements to fill.

value: Reg

The value of the filled elements.

TableFillExact

Variant of Instruction::TableFill with 16-bit constant len index.

Encoding

Followed by Instruction::TableIndex encoding the Wasm table instance.

Fields

dst: Reg

The start index of the table to fill.

len: Const16<u64>

The number of elements to fill.

value: Reg

The value of the filled elements.

TableFillAtExact

Variant of Instruction::TableFill with 16-bit constant dst and len fields.

Encoding

Followed by Instruction::TableIndex encoding the Wasm table instance.

Fields

dst: Const16<u64>

The start index of the table to fill.

len: Const16<u64>

The number of elements to fill.

value: Reg

The value of the filled elements.

TableGrow

Wasm table.grow <table> instruction.

Encoding

Followed by Instruction::TableIndex encoding the Wasm table instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

delta: Reg

The number of elements to add to the table.

value: Reg

The value that is used to fill up the new cells.

TableGrowImm

Variant of Instruction::TableGrow with 16-bit constant delta.

Encoding

Followed by Instruction::TableIndex encoding the Wasm table instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

delta: Const16<u64>

The number of elements to add to the table.

value: Reg

The value that is used to fill up the new cells.

ElemDrop

A Wasm elem.drop equalivalent Wasmi instruction.

Fields

index: Elem

DataDrop

A Wasm data.drop equalivalent Wasmi instruction.

Fields

index: Data

MemorySize

Wasm memory.size instruction.

Fields

result: Reg

The register(s) storing the result of the instruction.

memory: Memory

The index identifying the Wasm linear memory for the instruction.

MemoryGrow

Wasm memory.grow instruction.

Encoding

Followed by Instruction::MemoryIndex encoding the Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

delta: Reg

The number of pages to add to the memory.

MemoryGrowBy

Variant of Instruction::MemoryGrow with 16-bit constant delta.

Encoding

Followed by Instruction::MemoryIndex encoding the Wasm memory instance.

Fields

result: Reg

The register(s) storing the result of the instruction.

delta: u32

The number of pages to add to the memory.

MemoryCopy

Wasm memory.copy instruction.

Copies elements from memory[src..src+len] to memory[dst..dst+len].

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the dst Wasm linear memory instance
2. Instruction::MemoryIndex: the src Wasm linear memory instance

Fields

dst: Reg

The start index of the dst memory.

src: Reg

The start index of the src memory.

len: Reg

The number of copied bytes.

MemoryCopyTo

Variant of Instruction::MemoryCopy with a constant 16-bit dst index.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the dst Wasm linear memory instance
2. Instruction::MemoryIndex: the src Wasm linear memory instance

Fields

dst: Const16<u64>

The start index of the dst memory.

src: Reg

The start index of the src memory.

len: Reg

The number of copied bytes.

MemoryCopyFrom

Variant of Instruction::MemoryCopy with a constant 16-bit src index.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the dst Wasm linear memory instance
2. Instruction::MemoryIndex: the src Wasm linear memory instance

Fields

dst: Reg

The start index of the dst memory.

src: Const16<u64>

The start index of the src memory.

len: Reg

The number of copied bytes.

MemoryCopyFromTo

Variant of Instruction::MemoryCopy with a constant 16-bit dst and src indices.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the dst Wasm linear memory instance
2. Instruction::MemoryIndex: the src Wasm linear memory instance

Fields

dst: Const16<u64>

The start index of the dst memory.

src: Const16<u64>

The start index of the src memory.

len: Reg

The number of copied bytes.

MemoryCopyExact

Variant of Instruction::MemoryCopy with a constant 16-bit len field.

Note

This instruction copies exactly len elements between the memories.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the dst Wasm linear memory instance
2. Instruction::MemoryIndex: the src Wasm linear memory instance

Fields

dst: Reg

The start index of the dst memory.

src: Reg

The start index of the src memory.

len: Const16<u64>

The number of copied bytes.

MemoryCopyToExact

Variant of Instruction::MemoryCopy with a constant 16-bit len and dst.

Note

This instruction copies exactly len elements between the memories.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the dst Wasm linear memory instance
2. Instruction::MemoryIndex: the src Wasm linear memory instance

Fields

dst: Const16<u64>

The start index of the dst memory.

src: Reg

The start index of the src memory.

len: Const16<u64>

The number of copied bytes.

MemoryCopyFromExact

Variant of Instruction::MemoryCopy with a constant 16-bit len and src.

Note

This instruction copies exactly len elements between the memories.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the dst Wasm linear memory instance
2. Instruction::MemoryIndex: the src Wasm linear memory instance

Fields

dst: Reg

The start index of the dst memory.

src: Const16<u64>

The start index of the src memory.

len: Const16<u64>

The number of copied bytes.

MemoryCopyFromToExact

Variant of Instruction::MemoryCopy with a constant 16-bit len and src.

Note

This instruction copies exactly len elements between the memories.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the dst Wasm linear memory instance
2. Instruction::MemoryIndex: the src Wasm linear memory instance

Fields

dst: Const16<u64>

The start index of the dst memory.

src: Const16<u64>

The start index of the src memory.

len: Const16<u64>

The number of copied bytes.

MemoryFill

Wasm memory.fill instruction.

Sets bytes of memory[dst..dst+len] to value.

Encoding

Followed by Instruction::MemoryIndex encoding the Wasm memory instance.

Fields

dst: Reg

The start index of the memory to fill.

value: Reg

The byte value used to fill the memory.

len: Reg

The number of bytes to fill.

MemoryFillAt

Variant of Instruction::MemoryFill with 16-bit constant dst index.

Encoding

Followed by Instruction::MemoryIndex encoding the Wasm memory instance.

Fields

dst: Const16<u64>

The start index of the memory to fill.

value: Reg

The byte value used to fill the memory.

len: Reg

The number of bytes to fill.

MemoryFillImm

Variant of Instruction::MemoryFill with constant fill value.

Encoding

Followed by Instruction::MemoryIndex encoding the Wasm memory instance.

Fields

dst: Reg

The start index of the memory to fill.

value: u8

The byte value used to fill the memory.

len: Reg

The number of bytes to fill.

MemoryFillExact

Variant of Instruction::MemoryFill with 16-bit constant len value.

Encoding

Followed by Instruction::MemoryIndex encoding the Wasm memory instance.

Fields

dst: Reg

The start index of the memory to fill.

value: Reg

The byte value used to fill the memory.

len: Const16<u64>

The number of bytes to fill.

MemoryFillAtImm

Variant of Instruction::MemoryFill with constant dst index and value.

Encoding

Followed by Instruction::MemoryIndex encoding the Wasm memory instance.

Fields

dst: Const16<u64>

The start index of the memory to fill.

value: u8

The byte value used to fill the memory.

len: Reg

The number of bytes to fill.

MemoryFillAtExact

Variant of Instruction::MemoryFill with constant dst index and len.

Encoding

Followed by Instruction::MemoryIndex encoding the Wasm memory instance.

Fields

dst: Const16<u64>

The start index of the memory to fill.

value: Reg

The byte value used to fill the memory.

len: Const16<u64>

The number of bytes to fill.

MemoryFillImmExact

Variant of Instruction::MemoryFill with constant fill value and len.

Encoding

Followed by Instruction::MemoryIndex encoding the Wasm memory instance.

Fields

dst: Reg

The start index of the memory to fill.

value: u8

The byte value used to fill the memory.

len: Const16<u64>

The number of bytes to fill.

MemoryFillAtImmExact

Variant of Instruction::MemoryFill with constant dst index, fill value and len.

Encoding

Followed by Instruction::MemoryIndex encoding the Wasm memory instance.

Fields

dst: Const16<u64>

The start index of the memory to fill.

value: u8

The byte value used to fill the memory.

len: Const16<u64>

The number of bytes to fill.

MemoryInit

Wasm memory.init <data> instruction.

Initializes bytes of memory[dst..dst+len] from data[src..src+len].

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the Wasm memory instance
2. Instruction::DataIndex: the data segment to initialize the memory

Fields

dst: Reg

The start index of the dst memory.

src: Reg

The start index of the src data segment.

len: Reg

The number of bytes to initialize.

MemoryInitTo

Variant of Instruction::MemoryInit with a constant 16-bit dst index.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the Wasm memory instance
2. Instruction::DataIndex: the data segment to initialize the memory

Fields

dst: Const16<u64>

The start index of the dst memory.

src: Reg

The start index of the src data segment.

len: Reg

The number of initialized bytes.

MemoryInitFrom

Variant of Instruction::MemoryInit with a constant 16-bit src index.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the Wasm memory instance
2. Instruction::DataIndex: the data segment to initialize the memory

Fields

dst: Reg

The start index of the dst memory.

src: Const16<u32>

The start index of the src data segment.

len: Reg

The number of initialized bytes.

MemoryInitFromTo

Variant of Instruction::MemoryInit with a constant 16-bit dst and src indices.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the Wasm memory instance
2. Instruction::DataIndex: the data segment to initialize the memory

Fields

dst: Const16<u64>

The start index of the dst memory.

src: Const16<u32>

The start index of the src data segment.

len: Reg

The number of initialized bytes.

MemoryInitExact

Variant of Instruction::MemoryInit with a constant 16-bit len field.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the Wasm memory instance
2. Instruction::DataIndex: the data segment to initialize the memory

Fields

dst: Reg

The start index of the dst memory.

src: Reg

The start index of the src data segment.

len: Const16<u32>

The number of initialized bytes.

MemoryInitToExact

Variant of Instruction::MemoryInit with a constant 16-bit len and dst.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the Wasm memory instance
2. Instruction::DataIndex: the data segment to initialize the memory

Fields

dst: Const16<u64>

The start index of the dst memory.

src: Reg

The start index of the src data segment.

len: Const16<u32>

The number of initialized bytes.

MemoryInitFromExact

Variant of Instruction::MemoryInit with a constant 16-bit len and src.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the Wasm memory instance
2. Instruction::DataIndex: the data segment to initialize the memory

Fields

dst: Reg

The start index of the dst memory.

src: Const16<u32>

The start index of the src data segment.

len: Const16<u32>

The number of initialized bytes.

MemoryInitFromToExact

Variant of Instruction::MemoryInit with a constant 16-bit len and src.

Encoding

This Instruction must be followed by

1. Instruction::MemoryIndex: the Wasm memory instance
2. Instruction::DataIndex: the data segment to initialize the memory

Fields

dst: Const16<u64>

The start index of the dst memory.

src: Const16<u32>

The start index of the src data segment.

len: Const16<u32>

The number of initialized bytes.

TableIndex

A Table instruction parameter.

Note

This Instruction only acts as a parameter to another one and will never be executed itself directly.

Fields

index: Table

MemoryIndex

A Memory instruction parameter.

Note

This Instruction only acts as a parameter to another one and will never be executed itself directly.

Fields

index: Memory

DataIndex

A Data instruction parameter.

Note

This Instruction only acts as a parameter to another one and will never be executed itself directly.

Fields

index: Data

ElemIndex

An Elem instruction parameter.

Note

This Instruction only acts as a parameter to another one and will never be executed itself directly.

Fields

index: Elem

Const32

A AnyConst32 instruction parameter.

Note

This Instruction only acts as a parameter to another one and will never be executed itself directly.

Fields

value: AnyConst32

I64Const32

A Const32<i64> instruction parameter.

Note

This Instruction only acts as a parameter to another one and will never be executed itself directly.

Fields

value: Const32<i64>

F64Const32

A Const32<f64> instruction parameter.

Note

This Instruction only acts as a parameter to another one and will never be executed itself directly.

Fields

value: Const32<f64>

BranchTableTarget

A Wasm br_table branching target which copies values before branching.

Encoding

This always follows

• Instruction::BranchTable1
• Instruction::BranchTable2
• Instruction::BranchTableSpan
• Instruction::BranchTableMany

Fields

results: RegSpan

The registers where the values are going to be copied.

offset: BranchOffset

The branching offset of the branch table target.

BranchTableTargetNonOverlapping

A Wasm br_table branching target which copies overlapping values before branching.

Encoding

This always follows

• Instruction::BranchTableSpan
• Instruction::BranchTableMany

Fields

results: RegSpan

The registers where the values are going to be copied.

offset: BranchOffset

The branching offset of the branch table target.

Imm16AndImm32

An instruction parameter with 16-bit and 32-bit immediate values.

Fields

imm16: AnyConst16

The 16-bit immediate value.

imm32: AnyConst32

The 32-bit immediate value.

RegisterAndImm32

An instruction parameter with a Reg and a 32-bit immediate value.

Fields

reg: Reg

The Reg parameter value.

imm: AnyConst32

The 32-bit immediate value.

RegisterSpan

A bounded RegSpan instruction parameter.

Fields

span: BoundedRegSpan

Register

A Reg instruction parameter.

Note

This Instruction only acts as a parameter to another one and will never be executed itself directly.

Fields

reg: Reg

Register2

Two Reg instruction parameters.

Note

This Instruction only acts as a parameter to another one and will never be executed itself directly.

Fields

regs: [Reg; 2]

Register3

Three Reg instruction parameters.

Note

This Instruction only acts as a parameter to another one and will never be executed itself directly.

Fields

regs: [Reg; 3]

RegisterList

Reg slice parameters.

Note

This Instruction only acts as a parameter to another one and will never be executed itself directly.

Encoding

This must always be followed by one of

• Instruction::Register
• Instruction::Register2
• Instruction::Register3

Fields

regs: [Reg; 3]

CallIndirectParams

Auxiliary Instruction to encode table access information for indirect call instructions.

Fields

index: Reg

The index of the called function in the table.

table: Table

The table which holds the called function at the index.

CallIndirectParamsImm16

Variant of Instruction::CallIndirectParams for 16-bit constant index parameter.

Fields

index: Const16<u64>

The index of the called function in the table.

table: Table

The table which holds the called function at the index.

Implementations

impl Instruction

pub fn trap(trap_code: impl Into<TrapCode>) -> Self

Creates a new Instruction::Trap.

pub fn consume_fuel(block_fuel: impl Into<BlockFuel>) -> Self

Creates a new Instruction::ConsumeFuel.

pub fn return() -> Self

Creates a new Instruction::Return.

pub fn return_reg(value: impl Into<Reg>) -> Self

Creates a new Instruction::ReturnReg.

pub fn return_reg2(values: impl Into<[Reg; 2]>) -> Self

Creates a new Instruction::ReturnReg2.

pub fn return_reg3(values: impl Into<[Reg; 3]>) -> Self

Creates a new Instruction::ReturnReg3.

pub fn return_imm32(value: impl Into<AnyConst32>) -> Self

Creates a new Instruction::ReturnImm32.

pub fn return_i64imm32(value: impl Into<Const32<i64>>) -> Self

Creates a new Instruction::ReturnI64Imm32.

pub fn return_f64imm32(value: impl Into<Const32<f64>>) -> Self

Creates a new Instruction::ReturnF64Imm32.

pub fn return_span(values: impl Into<BoundedRegSpan>) -> Self

Creates a new Instruction::ReturnSpan.

pub fn return_many(values: impl Into<[Reg; 3]>) -> Self

Creates a new Instruction::ReturnMany.

pub fn return_nez(condition: impl Into<Reg>) -> Self

Creates a new Instruction::ReturnNez.

pub fn return_nez_reg(condition: impl Into<Reg>, value: impl Into<Reg>) -> Self

Creates a new Instruction::ReturnNezReg.

pub fn return_nez_reg2( condition: impl Into<Reg>, values: impl Into<[Reg; 2]>, ) -> Self

Creates a new Instruction::ReturnNezReg2.

pub fn return_nez_imm32( condition: impl Into<Reg>, value: impl Into<AnyConst32>, ) -> Self

Creates a new Instruction::ReturnNezImm32.

pub fn return_nez_i64imm32( condition: impl Into<Reg>, value: impl Into<Const32<i64>>, ) -> Self

Creates a new Instruction::ReturnNezI64Imm32.

pub fn return_nez_f64imm32( condition: impl Into<Reg>, value: impl Into<Const32<f64>>, ) -> Self

Creates a new Instruction::ReturnNezF64Imm32.

pub fn return_nez_span( condition: impl Into<Reg>, values: impl Into<BoundedRegSpan>, ) -> Self

Creates a new Instruction::ReturnNezSpan.

pub fn return_nez_many( condition: impl Into<Reg>, values: impl Into<[Reg; 2]>, ) -> Self

Creates a new Instruction::ReturnNezMany.

pub fn branch(offset: impl Into<BranchOffset>) -> Self

Creates a new Instruction::Branch.

pub fn branch_cmp_fallback( lhs: impl Into<Reg>, rhs: impl Into<Reg>, params: impl Into<Reg>, ) -> Self

Creates a new Instruction::BranchCmpFallback.

pub fn branch_i32_and( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32And.

pub fn branch_i32_and_imm16( lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32AndImm16.

pub fn branch_i32_or( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32Or.

pub fn branch_i32_or_imm16( lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32OrImm16.

pub fn branch_i32_xor( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32Xor.

pub fn branch_i32_xor_imm16( lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32XorImm16.

pub fn branch_i32_and_eqz( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32AndEqz.

pub fn branch_i32_and_eqz_imm16( lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32AndEqzImm16.

pub fn branch_i32_or_eqz( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32OrEqz.

pub fn branch_i32_or_eqz_imm16( lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32OrEqzImm16.

pub fn branch_i32_xor_eqz( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32XorEqz.

pub fn branch_i32_xor_eqz_imm16( lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32XorEqzImm16.

pub fn branch_i32_eq( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32Eq.

pub fn branch_i32_eq_imm16( lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32EqImm16.

pub fn branch_i32_ne( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32Ne.

pub fn branch_i32_ne_imm16( lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32NeImm16.

pub fn branch_i32_lt_s( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LtS.

pub fn branch_i32_lt_s_imm16_lhs( lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LtSImm16Lhs.

pub fn branch_i32_lt_s_imm16_rhs( lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LtSImm16Rhs.

pub fn branch_i32_lt_u( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LtU.

pub fn branch_i32_lt_u_imm16_lhs( lhs: impl Into<Const16<u32>>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LtUImm16Lhs.

pub fn branch_i32_lt_u_imm16_rhs( lhs: impl Into<Reg>, rhs: impl Into<Const16<u32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LtUImm16Rhs.

pub fn branch_i32_le_s( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LeS.

pub fn branch_i32_le_s_imm16_lhs( lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LeSImm16Lhs.

pub fn branch_i32_le_s_imm16_rhs( lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LeSImm16Rhs.

pub fn branch_i32_le_u( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LeU.

pub fn branch_i32_le_u_imm16_lhs( lhs: impl Into<Const16<u32>>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LeUImm16Lhs.

pub fn branch_i32_le_u_imm16_rhs( lhs: impl Into<Reg>, rhs: impl Into<Const16<u32>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI32LeUImm16Rhs.

pub fn branch_i64_eq( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64Eq.

pub fn branch_i64_eq_imm16( lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64EqImm16.

pub fn branch_i64_ne( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64Ne.

pub fn branch_i64_ne_imm16( lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64NeImm16.

pub fn branch_i64_lt_s( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LtS.

pub fn branch_i64_lt_s_imm16_lhs( lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LtSImm16Lhs.

pub fn branch_i64_lt_s_imm16_rhs( lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LtSImm16Rhs.

pub fn branch_i64_lt_u( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LtU.

pub fn branch_i64_lt_u_imm16_lhs( lhs: impl Into<Const16<u64>>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LtUImm16Lhs.

pub fn branch_i64_lt_u_imm16_rhs( lhs: impl Into<Reg>, rhs: impl Into<Const16<u64>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LtUImm16Rhs.

pub fn branch_i64_le_s( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LeS.

pub fn branch_i64_le_s_imm16_lhs( lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LeSImm16Lhs.

pub fn branch_i64_le_s_imm16_rhs( lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LeSImm16Rhs.

pub fn branch_i64_le_u( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LeU.

pub fn branch_i64_le_u_imm16_lhs( lhs: impl Into<Const16<u64>>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LeUImm16Lhs.

pub fn branch_i64_le_u_imm16_rhs( lhs: impl Into<Reg>, rhs: impl Into<Const16<u64>>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchI64LeUImm16Rhs.

pub fn branch_f32_eq( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchF32Eq.

pub fn branch_f32_ne( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchF32Ne.

pub fn branch_f32_lt( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchF32Lt.

pub fn branch_f32_le( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchF32Le.

pub fn branch_f64_eq( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchF64Eq.

pub fn branch_f64_ne( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchF64Ne.

pub fn branch_f64_lt( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchF64Lt.

pub fn branch_f64_le( lhs: impl Into<Reg>, rhs: impl Into<Reg>, offset: impl Into<BranchOffset16>, ) -> Self

Creates a new Instruction::BranchF64Le.

pub fn branch_table_0( index: impl Into<Reg>, len_targets: impl Into<u32>, ) -> Self

Creates a new Instruction::BranchTable0.

pub fn branch_table_1( index: impl Into<Reg>, len_targets: impl Into<u32>, ) -> Self

Creates a new Instruction::BranchTable1.

pub fn branch_table_2( index: impl Into<Reg>, len_targets: impl Into<u32>, ) -> Self

Creates a new Instruction::BranchTable2.

pub fn branch_table_3( index: impl Into<Reg>, len_targets: impl Into<u32>, ) -> Self

Creates a new Instruction::BranchTable3.

pub fn branch_table_span( index: impl Into<Reg>, len_targets: impl Into<u32>, ) -> Self

Creates a new Instruction::BranchTableSpan.

pub fn branch_table_many( index: impl Into<Reg>, len_targets: impl Into<u32>, ) -> Self

Creates a new Instruction::BranchTableMany.

pub fn copy(result: impl Into<Reg>, value: impl Into<Reg>) -> Self

Creates a new Instruction::Copy.

pub fn copy2( results: impl Into<FixedRegSpan<2>>, values: impl Into<[Reg; 2]>, ) -> Self

Creates a new Instruction::Copy2.

pub fn copy_imm32(result: impl Into<Reg>, value: impl Into<AnyConst32>) -> Self

Creates a new Instruction::CopyImm32.

pub fn copy_i64imm32( result: impl Into<Reg>, value: impl Into<Const32<i64>>, ) -> Self

Creates a new Instruction::CopyI64Imm32.

pub fn copy_f64imm32( result: impl Into<Reg>, value: impl Into<Const32<f64>>, ) -> Self

Creates a new Instruction::CopyF64Imm32.

pub fn copy_span( results: impl Into<RegSpan>, values: impl Into<RegSpan>, len: impl Into<u16>, ) -> Self

Creates a new Instruction::CopySpan.

pub fn copy_span_non_overlapping( results: impl Into<RegSpan>, values: impl Into<RegSpan>, len: impl Into<u16>, ) -> Self

Creates a new Instruction::CopySpanNonOverlapping.

pub fn copy_many( results: impl Into<RegSpan>, values: impl Into<[Reg; 2]>, ) -> Self

Creates a new Instruction::CopyMany.

pub fn copy_many_non_overlapping( results: impl Into<RegSpan>, values: impl Into<[Reg; 2]>, ) -> Self

Creates a new Instruction::CopyManyNonOverlapping.

pub fn return_call_internal_0(func: impl Into<InternalFunc>) -> Self

Creates a new Instruction::ReturnCallInternal0.

pub fn return_call_internal(func: impl Into<InternalFunc>) -> Self

Creates a new Instruction::ReturnCallInternal.

pub fn return_call_imported_0(func: impl Into<Func>) -> Self

Creates a new Instruction::ReturnCallImported0.

pub fn return_call_imported(func: impl Into<Func>) -> Self

Creates a new Instruction::ReturnCallImported.

pub fn return_call_indirect_0(func_type: impl Into<FuncType>) -> Self

Creates a new Instruction::ReturnCallIndirect0.

pub fn return_call_indirect_0_imm16(func_type: impl Into<FuncType>) -> Self

Creates a new Instruction::ReturnCallIndirect0Imm16.

pub fn return_call_indirect(func_type: impl Into<FuncType>) -> Self

Creates a new Instruction::ReturnCallIndirect.

pub fn return_call_indirect_imm16(func_type: impl Into<FuncType>) -> Self

Creates a new Instruction::ReturnCallIndirectImm16.

pub fn call_internal_0( results: impl Into<RegSpan>, func: impl Into<InternalFunc>, ) -> Self

Creates a new Instruction::CallInternal0.

pub fn call_internal( results: impl Into<RegSpan>, func: impl Into<InternalFunc>, ) -> Self

Creates a new Instruction::CallInternal.

pub fn call_imported_0( results: impl Into<RegSpan>, func: impl Into<Func>, ) -> Self

Creates a new Instruction::CallImported0.

pub fn call_imported(results: impl Into<RegSpan>, func: impl Into<Func>) -> Self

Creates a new Instruction::CallImported.

pub fn call_indirect_0( results: impl Into<RegSpan>, func_type: impl Into<FuncType>, ) -> Self

Creates a new Instruction::CallIndirect0.

pub fn call_indirect_0_imm16( results: impl Into<RegSpan>, func_type: impl Into<FuncType>, ) -> Self

Creates a new Instruction::CallIndirect0Imm16.

pub fn call_indirect( results: impl Into<RegSpan>, func_type: impl Into<FuncType>, ) -> Self

Creates a new Instruction::CallIndirect.

pub fn call_indirect_imm16( results: impl Into<RegSpan>, func_type: impl Into<FuncType>, ) -> Self

Creates a new Instruction::CallIndirectImm16.

pub fn select(result: impl Into<Reg>, lhs: impl Into<Reg>) -> Self

Creates a new Instruction::Select.

pub fn select_imm32_rhs(result: impl Into<Reg>, lhs: impl Into<Reg>) -> Self

Creates a new Instruction::SelectImm32Rhs.

pub fn select_imm32_lhs( result: impl Into<Reg>, lhs: impl Into<AnyConst32>, ) -> Self

Creates a new Instruction::SelectImm32Lhs.

pub fn select_imm32(result: impl Into<Reg>, lhs: impl Into<AnyConst32>) -> Self

Creates a new Instruction::SelectImm32.

pub fn select_i64imm32_rhs(result: impl Into<Reg>, lhs: impl Into<Reg>) -> Self

Creates a new Instruction::SelectI64Imm32Rhs.

pub fn select_i64imm32_lhs( result: impl Into<Reg>, lhs: impl Into<Const32<i64>>, ) -> Self

Creates a new Instruction::SelectI64Imm32Lhs.

pub fn select_i64imm32( result: impl Into<Reg>, lhs: impl Into<Const32<i64>>, ) -> Self

Creates a new Instruction::SelectI64Imm32.

pub fn select_f64imm32_rhs(result: impl Into<Reg>, lhs: impl Into<Reg>) -> Self

Creates a new Instruction::SelectF64Imm32Rhs.

pub fn select_f64imm32_lhs( result: impl Into<Reg>, lhs: impl Into<Const32<f64>>, ) -> Self

Creates a new Instruction::SelectF64Imm32Lhs.

pub fn select_f64imm32( result: impl Into<Reg>, lhs: impl Into<Const32<f64>>, ) -> Self

Creates a new Instruction::SelectF64Imm32.

pub fn ref_func(result: impl Into<Reg>, func: impl Into<Func>) -> Self

Creates a new Instruction::RefFunc.

pub fn global_get(result: impl Into<Reg>, global: impl Into<Global>) -> Self

Creates a new Instruction::GlobalGet.

pub fn global_set(input: impl Into<Reg>, global: impl Into<Global>) -> Self

Creates a new Instruction::GlobalSet.

pub fn global_set_i32imm16( input: impl Into<Const16<i32>>, global: impl Into<Global>, ) -> Self

Creates a new Instruction::GlobalSetI32Imm16.

pub fn global_set_i64imm16( input: impl Into<Const16<i64>>, global: impl Into<Global>, ) -> Self

Creates a new Instruction::GlobalSetI64Imm16.

pub fn load32(result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>) -> Self

Creates a new Instruction::Load32.

pub fn load32_at(result: impl Into<Reg>, address: impl Into<Address32>) -> Self

Creates a new Instruction::Load32At.

pub fn load32_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::Load32Offset16.

pub fn load64(result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>) -> Self

Creates a new Instruction::Load64.

pub fn load64_at(result: impl Into<Reg>, address: impl Into<Address32>) -> Self

Creates a new Instruction::Load64At.

pub fn load64_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::Load64Offset16.

pub fn i32_load8_s( result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I32Load8s.

pub fn i32_load8_s_at( result: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I32Load8sAt.

pub fn i32_load8_s_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::I32Load8sOffset16.

pub fn i32_load8_u( result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I32Load8u.

pub fn i32_load8_u_at( result: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I32Load8uAt.

pub fn i32_load8_u_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::I32Load8uOffset16.

pub fn i32_load16_s( result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I32Load16s.

pub fn i32_load16_s_at( result: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I32Load16sAt.

pub fn i32_load16_s_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::I32Load16sOffset16.

pub fn i32_load16_u( result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I32Load16u.

pub fn i32_load16_u_at( result: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I32Load16uAt.

pub fn i32_load16_u_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::I32Load16uOffset16.

pub fn i64_load8_s( result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64Load8s.

pub fn i64_load8_s_at( result: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Load8sAt.

pub fn i64_load8_s_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::I64Load8sOffset16.

pub fn i64_load8_u( result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64Load8u.

pub fn i64_load8_u_at( result: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Load8uAt.

pub fn i64_load8_u_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::I64Load8uOffset16.

pub fn i64_load16_s( result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64Load16s.

pub fn i64_load16_s_at( result: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Load16sAt.

pub fn i64_load16_s_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::I64Load16sOffset16.

pub fn i64_load16_u( result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64Load16u.

pub fn i64_load16_u_at( result: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Load16uAt.

pub fn i64_load16_u_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::I64Load16uOffset16.

pub fn i64_load32_s( result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64Load32s.

pub fn i64_load32_s_at( result: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Load32sAt.

pub fn i64_load32_s_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::I64Load32sOffset16.

pub fn i64_load32_u( result: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64Load32u.

pub fn i64_load32_u_at( result: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Load32uAt.

pub fn i64_load32_u_offset16( result: impl Into<Reg>, ptr: impl Into<Reg>, offset: impl Into<Offset16>, ) -> Self

Creates a new Instruction::I64Load32uOffset16.

pub fn store32(ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>) -> Self

Creates a new Instruction::Store32.

pub fn store32_offset16( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::Store32Offset16.

pub fn store32_at(value: impl Into<Reg>, address: impl Into<Address32>) -> Self

Creates a new Instruction::Store32At.

pub fn store64(ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>) -> Self

Creates a new Instruction::Store64.

pub fn store64_offset16( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::Store64Offset16.

pub fn store64_at(value: impl Into<Reg>, address: impl Into<Address32>) -> Self

Creates a new Instruction::Store64At.

pub fn i32_store_imm16( ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I32StoreImm16.

pub fn i32_store_offset16_imm16( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32StoreOffset16Imm16.

pub fn i32_store_at_imm16( value: impl Into<Const16<i32>>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I32StoreAtImm16.

pub fn i32_store8(ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>) -> Self

Creates a new Instruction::I32Store8.

pub fn i32_store8_imm( ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I32Store8Imm.

pub fn i32_store8_offset16( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Store8Offset16.

pub fn i32_store8_offset16_imm( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<i8>, ) -> Self

Creates a new Instruction::I32Store8Offset16Imm.

pub fn i32_store8_at( value: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I32Store8At.

pub fn i32_store8_at_imm( value: impl Into<i8>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I32Store8AtImm.

pub fn i32_store16( ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I32Store16.

pub fn i32_store16_imm( ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I32Store16Imm.

pub fn i32_store16_offset16( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Store16Offset16.

pub fn i32_store16_offset16_imm( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<i16>, ) -> Self

Creates a new Instruction::I32Store16Offset16Imm.

pub fn i32_store16_at( value: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I32Store16At.

pub fn i32_store16_at_imm( value: impl Into<i16>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I32Store16AtImm.

pub fn i64_store_imm16( ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64StoreImm16.

pub fn i64_store_offset16_imm16( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<Const16<i64>>, ) -> Self

Creates a new Instruction::I64StoreOffset16Imm16.

pub fn i64_store_at_imm16( value: impl Into<Const16<i64>>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64StoreAtImm16.

pub fn i64_store8(ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>) -> Self

Creates a new Instruction::I64Store8.

pub fn i64_store8_imm( ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64Store8Imm.

pub fn i64_store8_offset16( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Store8Offset16.

pub fn i64_store8_offset16_imm( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<i8>, ) -> Self

Creates a new Instruction::I64Store8Offset16Imm.

pub fn i64_store8_at( value: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Store8At.

pub fn i64_store8_at_imm( value: impl Into<i8>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Store8AtImm.

pub fn i64_store16( ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64Store16.

pub fn i64_store16_imm( ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64Store16Imm.

pub fn i64_store16_offset16( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Store16Offset16.

pub fn i64_store16_offset16_imm( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<i16>, ) -> Self

Creates a new Instruction::I64Store16Offset16Imm.

pub fn i64_store16_at( value: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Store16At.

pub fn i64_store16_at_imm( value: impl Into<i16>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Store16AtImm.

pub fn i64_store32( ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64Store32.

pub fn i64_store32_imm16( ptr: impl Into<Reg>, offset_lo: impl Into<Offset64Lo>, ) -> Self

Creates a new Instruction::I64Store32Imm16.

pub fn i64_store32_offset16( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Store32Offset16.

pub fn i64_store32_offset16_imm16( ptr: impl Into<Reg>, offset: impl Into<Offset16>, value: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I64Store32Offset16Imm16.

pub fn i64_store32_at( value: impl Into<Reg>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Store32At.

pub fn i64_store32_at_imm16( value: impl Into<Const16<i32>>, address: impl Into<Address32>, ) -> Self

Creates a new Instruction::I64Store32AtImm16.

pub fn i32_eq( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Eq.

pub fn i32_eq_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32EqImm16.

pub fn i32_ne( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Ne.

pub fn i32_ne_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32NeImm16.

pub fn i32_lt_s( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32LtS.

pub fn i32_lt_s_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32LtSImm16Lhs.

pub fn i32_lt_s_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32LtSImm16Rhs.

pub fn i32_lt_u( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32LtU.

pub fn i32_lt_u_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<u32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32LtUImm16Lhs.

pub fn i32_lt_u_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<u32>>, ) -> Self

Creates a new Instruction::I32LtUImm16Rhs.

pub fn i32_le_s( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32LeS.

pub fn i32_le_s_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32LeSImm16Lhs.

pub fn i32_le_s_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32LeSImm16Rhs.

pub fn i32_le_u( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32LeU.

pub fn i32_le_u_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<u32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32LeUImm16Lhs.

pub fn i32_le_u_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<u32>>, ) -> Self

Creates a new Instruction::I32LeUImm16Rhs.

pub fn i64_eq( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Eq.

pub fn i64_eq_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, ) -> Self

Creates a new Instruction::I64EqImm16.

pub fn i64_ne( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Ne.

pub fn i64_ne_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, ) -> Self

Creates a new Instruction::I64NeImm16.

pub fn i64_lt_s( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64LtS.

pub fn i64_lt_s_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64LtSImm16Lhs.

pub fn i64_lt_s_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, ) -> Self

Creates a new Instruction::I64LtSImm16Rhs.

pub fn i64_lt_u( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64LtU.

pub fn i64_lt_u_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<u64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64LtUImm16Lhs.

pub fn i64_lt_u_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::I64LtUImm16Rhs.

pub fn i64_le_s( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64LeS.

pub fn i64_le_s_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64LeSImm16Lhs.

pub fn i64_le_s_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, ) -> Self

Creates a new Instruction::I64LeSImm16Rhs.

pub fn i64_le_u( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64LeU.

pub fn i64_le_u_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<u64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64LeUImm16Lhs.

pub fn i64_le_u_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::I64LeUImm16Rhs.

pub fn f32_eq( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F32Eq.

pub fn f32_ne( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F32Ne.

pub fn f32_lt( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F32Lt.

pub fn f32_le( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F32Le.

pub fn f64_eq( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F64Eq.

pub fn f64_ne( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F64Ne.

pub fn f64_lt( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F64Lt.

pub fn f64_le( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F64Le.

pub fn i32_clz(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I32Clz.

pub fn i32_ctz(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I32Ctz.

pub fn i32_popcnt(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I32Popcnt.

pub fn i32_add( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Add.

pub fn i32_add_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32AddImm16.

pub fn i32_sub( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Sub.

pub fn i32_sub_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32SubImm16Lhs.

pub fn i32_mul( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Mul.

pub fn i32_mul_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32MulImm16.

pub fn i32_div_s( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32DivS.

pub fn i32_div_s_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<NonZeroI32>>, ) -> Self

Creates a new Instruction::I32DivSImm16Rhs.

pub fn i32_div_s_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32DivSImm16Lhs.

pub fn i32_div_u( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32DivU.

pub fn i32_div_u_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<NonZeroU32>>, ) -> Self

Creates a new Instruction::I32DivUImm16Rhs.

pub fn i32_div_u_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<u32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32DivUImm16Lhs.

pub fn i32_rem_s( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32RemS.

pub fn i32_rem_s_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<NonZeroI32>>, ) -> Self

Creates a new Instruction::I32RemSImm16Rhs.

pub fn i32_rem_s_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32RemSImm16Lhs.

pub fn i32_rem_u( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32RemU.

pub fn i32_rem_u_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<NonZeroU32>>, ) -> Self

Creates a new Instruction::I32RemUImm16Rhs.

pub fn i32_rem_u_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<u32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32RemUImm16Lhs.

pub fn i32_and( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32And.

pub fn i32_and_eqz( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32AndEqz.

pub fn i32_and_eqz_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32AndEqzImm16.

pub fn i32_and_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32AndImm16.

pub fn i32_or( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Or.

pub fn i32_or_eqz( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32OrEqz.

pub fn i32_or_eqz_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32OrEqzImm16.

pub fn i32_or_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32OrImm16.

pub fn i32_xor( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Xor.

pub fn i32_xor_eqz( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32XorEqz.

pub fn i32_xor_eqz_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32XorEqzImm16.

pub fn i32_xor_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i32>>, ) -> Self

Creates a new Instruction::I32XorImm16.

pub fn i32_shl( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Shl.

pub fn i32_shl_by( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<ShiftAmount<i32>>, ) -> Self

Creates a new Instruction::I32ShlBy.

pub fn i32_shl_imm16( result: impl Into<Reg>, lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32ShlImm16.

pub fn i32_shr_u( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32ShrU.

pub fn i32_shr_u_by( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<ShiftAmount<i32>>, ) -> Self

Creates a new Instruction::I32ShrUBy.

pub fn i32_shr_u_imm16( result: impl Into<Reg>, lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32ShrUImm16.

pub fn i32_shr_s( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32ShrS.

pub fn i32_shr_s_by( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<ShiftAmount<i32>>, ) -> Self

Creates a new Instruction::I32ShrSBy.

pub fn i32_shr_s_imm16( result: impl Into<Reg>, lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32ShrSImm16.

pub fn i32_rotl( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Rotl.

pub fn i32_rotl_by( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<ShiftAmount<i32>>, ) -> Self

Creates a new Instruction::I32RotlBy.

pub fn i32_rotl_imm16( result: impl Into<Reg>, lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32RotlImm16.

pub fn i32_rotr( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32Rotr.

pub fn i32_rotr_by( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<ShiftAmount<i32>>, ) -> Self

Creates a new Instruction::I32RotrBy.

pub fn i32_rotr_imm16( result: impl Into<Reg>, lhs: impl Into<Const16<i32>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32RotrImm16.

pub fn i64_clz(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I64Clz.

pub fn i64_ctz(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I64Ctz.

pub fn i64_popcnt(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I64Popcnt.

pub fn i64_add( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Add.

pub fn i64_add_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, ) -> Self

Creates a new Instruction::I64AddImm16.

pub fn i64_sub( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Sub.

pub fn i64_sub_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64SubImm16Lhs.

pub fn i64_mul( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Mul.

pub fn i64_mul_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, ) -> Self

Creates a new Instruction::I64MulImm16.

pub fn i64_div_s( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64DivS.

pub fn i64_div_s_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<NonZeroI64>>, ) -> Self

Creates a new Instruction::I64DivSImm16Rhs.

pub fn i64_div_s_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64DivSImm16Lhs.

pub fn i64_div_u( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64DivU.

pub fn i64_div_u_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<NonZeroU64>>, ) -> Self

Creates a new Instruction::I64DivUImm16Rhs.

pub fn i64_div_u_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<u64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64DivUImm16Lhs.

pub fn i64_rem_s( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64RemS.

pub fn i64_rem_s_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<NonZeroI64>>, ) -> Self

Creates a new Instruction::I64RemSImm16Rhs.

pub fn i64_rem_s_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64RemSImm16Lhs.

pub fn i64_rem_u( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64RemU.

pub fn i64_rem_u_imm16_rhs( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<NonZeroU64>>, ) -> Self

Creates a new Instruction::I64RemUImm16Rhs.

pub fn i64_rem_u_imm16_lhs( result: impl Into<Reg>, lhs: impl Into<Const16<u64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64RemUImm16Lhs.

pub fn i64_and( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64And.

pub fn i64_and_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, ) -> Self

Creates a new Instruction::I64AndImm16.

pub fn i64_or( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Or.

pub fn i64_or_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, ) -> Self

Creates a new Instruction::I64OrImm16.

pub fn i64_xor( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Xor.

pub fn i64_xor_imm16( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Const16<i64>>, ) -> Self

Creates a new Instruction::I64XorImm16.

pub fn i64_shl( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Shl.

pub fn i64_shl_by( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<ShiftAmount<i64>>, ) -> Self

Creates a new Instruction::I64ShlBy.

pub fn i64_shl_imm16( result: impl Into<Reg>, lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64ShlImm16.

pub fn i64_shr_u( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64ShrU.

pub fn i64_shr_u_by( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<ShiftAmount<i64>>, ) -> Self

Creates a new Instruction::I64ShrUBy.

pub fn i64_shr_u_imm16( result: impl Into<Reg>, lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64ShrUImm16.

pub fn i64_shr_s( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64ShrS.

pub fn i64_shr_s_by( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<ShiftAmount<i64>>, ) -> Self

Creates a new Instruction::I64ShrSBy.

pub fn i64_shr_s_imm16( result: impl Into<Reg>, lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64ShrSImm16.

pub fn i64_rotl( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Rotl.

pub fn i64_rotl_by( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<ShiftAmount<i64>>, ) -> Self

Creates a new Instruction::I64RotlBy.

pub fn i64_rotl_imm16( result: impl Into<Reg>, lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64RotlImm16.

pub fn i64_rotr( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64Rotr.

pub fn i64_rotr_by( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<ShiftAmount<i64>>, ) -> Self

Creates a new Instruction::I64RotrBy.

pub fn i64_rotr_imm16( result: impl Into<Reg>, lhs: impl Into<Const16<i64>>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64RotrImm16.

pub fn i32_wrap_i64(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I32WrapI64.

pub fn i32_extend8_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I32Extend8S.

pub fn i32_extend16_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I32Extend16S.

pub fn i64_extend8_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I64Extend8S.

pub fn i64_extend16_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I64Extend16S.

pub fn i64_extend32_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I64Extend32S.

pub fn f32_abs(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32Abs.

pub fn f32_neg(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32Neg.

pub fn f32_ceil(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32Ceil.

pub fn f32_floor(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32Floor.

pub fn f32_trunc(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32Trunc.

pub fn f32_nearest(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32Nearest.

pub fn f32_sqrt(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32Sqrt.

pub fn f32_add( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F32Add.

pub fn f32_sub( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F32Sub.

pub fn f32_mul( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F32Mul.

pub fn f32_div( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F32Div.

pub fn f32_min( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F32Min.

pub fn f32_max( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F32Max.

pub fn f32_copysign( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F32Copysign.

pub fn f32_copysign_imm( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Sign<f32>>, ) -> Self

Creates a new Instruction::F32CopysignImm.

pub fn f64_abs(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64Abs.

pub fn f64_neg(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64Neg.

pub fn f64_ceil(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64Ceil.

pub fn f64_floor(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64Floor.

pub fn f64_trunc(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64Trunc.

pub fn f64_nearest(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64Nearest.

pub fn f64_sqrt(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64Sqrt.

pub fn f64_add( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F64Add.

pub fn f64_sub( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F64Sub.

pub fn f64_mul( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F64Mul.

pub fn f64_div( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F64Div.

pub fn f64_min( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F64Min.

pub fn f64_max( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F64Max.

pub fn f64_copysign( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Reg>, ) -> Self

Creates a new Instruction::F64Copysign.

pub fn f64_copysign_imm( result: impl Into<Reg>, lhs: impl Into<Reg>, rhs: impl Into<Sign<f64>>, ) -> Self

Creates a new Instruction::F64CopysignImm.

pub fn i32_trunc_f32_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I32TruncF32S.

pub fn i32_trunc_f32_u(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I32TruncF32U.

pub fn i32_trunc_f64_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I32TruncF64S.

pub fn i32_trunc_f64_u(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I32TruncF64U.

pub fn i64_trunc_f32_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I64TruncF32S.

pub fn i64_trunc_f32_u(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I64TruncF32U.

pub fn i64_trunc_f64_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I64TruncF64S.

pub fn i64_trunc_f64_u(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::I64TruncF64U.

pub fn i32_trunc_sat_f32_s( result: impl Into<Reg>, input: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32TruncSatF32S.

pub fn i32_trunc_sat_f32_u( result: impl Into<Reg>, input: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32TruncSatF32U.

pub fn i32_trunc_sat_f64_s( result: impl Into<Reg>, input: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32TruncSatF64S.

pub fn i32_trunc_sat_f64_u( result: impl Into<Reg>, input: impl Into<Reg>, ) -> Self

Creates a new Instruction::I32TruncSatF64U.

pub fn i64_trunc_sat_f32_s( result: impl Into<Reg>, input: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64TruncSatF32S.

pub fn i64_trunc_sat_f32_u( result: impl Into<Reg>, input: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64TruncSatF32U.

pub fn i64_trunc_sat_f64_s( result: impl Into<Reg>, input: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64TruncSatF64S.

pub fn i64_trunc_sat_f64_u( result: impl Into<Reg>, input: impl Into<Reg>, ) -> Self

Creates a new Instruction::I64TruncSatF64U.

pub fn f32_demote_f64(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32DemoteF64.

pub fn f64_promote_f32(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64PromoteF32.

pub fn f32_convert_i32_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32ConvertI32S.

pub fn f32_convert_i32_u(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32ConvertI32U.

pub fn f32_convert_i64_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32ConvertI64S.

pub fn f32_convert_i64_u(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F32ConvertI64U.

pub fn f64_convert_i32_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64ConvertI32S.

pub fn f64_convert_i32_u(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64ConvertI32U.

pub fn f64_convert_i64_s(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64ConvertI64S.

pub fn f64_convert_i64_u(result: impl Into<Reg>, input: impl Into<Reg>) -> Self

Creates a new Instruction::F64ConvertI64U.

pub fn table_get(result: impl Into<Reg>, index: impl Into<Reg>) -> Self

Creates a new Instruction::TableGet.

pub fn table_get_imm( result: impl Into<Reg>, index: impl Into<Const32<u64>>, ) -> Self

Creates a new Instruction::TableGetImm.

pub fn table_size(result: impl Into<Reg>, table: impl Into<Table>) -> Self

Creates a new Instruction::TableSize.

pub fn table_set(index: impl Into<Reg>, value: impl Into<Reg>) -> Self

Creates a new Instruction::TableSet.

pub fn table_set_at( value: impl Into<Reg>, index: impl Into<Const32<u64>>, ) -> Self

Creates a new Instruction::TableSetAt.

pub fn table_copy( dst: impl Into<Reg>, src: impl Into<Reg>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableCopy.

pub fn table_copy_to( dst: impl Into<Const16<u64>>, src: impl Into<Reg>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableCopyTo.

pub fn table_copy_from( dst: impl Into<Reg>, src: impl Into<Const16<u64>>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableCopyFrom.

pub fn table_copy_from_to( dst: impl Into<Const16<u64>>, src: impl Into<Const16<u64>>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableCopyFromTo.

pub fn table_copy_exact( dst: impl Into<Reg>, src: impl Into<Reg>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::TableCopyExact.

pub fn table_copy_to_exact( dst: impl Into<Const16<u64>>, src: impl Into<Reg>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::TableCopyToExact.

pub fn table_copy_from_exact( dst: impl Into<Reg>, src: impl Into<Const16<u64>>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::TableCopyFromExact.

pub fn table_copy_from_to_exact( dst: impl Into<Const16<u64>>, src: impl Into<Const16<u64>>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::TableCopyFromToExact.

pub fn table_init( dst: impl Into<Reg>, src: impl Into<Reg>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableInit.

pub fn table_init_to( dst: impl Into<Const16<u64>>, src: impl Into<Reg>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableInitTo.

pub fn table_init_from( dst: impl Into<Reg>, src: impl Into<Const16<u32>>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableInitFrom.

pub fn table_init_from_to( dst: impl Into<Const16<u64>>, src: impl Into<Const16<u32>>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableInitFromTo.

pub fn table_init_exact( dst: impl Into<Reg>, src: impl Into<Reg>, len: impl Into<Const16<u32>>, ) -> Self

Creates a new Instruction::TableInitExact.

pub fn table_init_to_exact( dst: impl Into<Const16<u64>>, src: impl Into<Reg>, len: impl Into<Const16<u32>>, ) -> Self

Creates a new Instruction::TableInitToExact.

pub fn table_init_from_exact( dst: impl Into<Reg>, src: impl Into<Const16<u32>>, len: impl Into<Const16<u32>>, ) -> Self

Creates a new Instruction::TableInitFromExact.

pub fn table_init_from_to_exact( dst: impl Into<Const16<u64>>, src: impl Into<Const16<u32>>, len: impl Into<Const16<u32>>, ) -> Self

Creates a new Instruction::TableInitFromToExact.

pub fn table_fill( dst: impl Into<Reg>, len: impl Into<Reg>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableFill.

pub fn table_fill_at( dst: impl Into<Const16<u64>>, len: impl Into<Reg>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableFillAt.

pub fn table_fill_exact( dst: impl Into<Reg>, len: impl Into<Const16<u64>>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableFillExact.

pub fn table_fill_at_exact( dst: impl Into<Const16<u64>>, len: impl Into<Const16<u64>>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableFillAtExact.

pub fn table_grow( result: impl Into<Reg>, delta: impl Into<Reg>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableGrow.

pub fn table_grow_imm( result: impl Into<Reg>, delta: impl Into<Const16<u64>>, value: impl Into<Reg>, ) -> Self

Creates a new Instruction::TableGrowImm.

pub fn elem_drop(index: impl Into<Elem>) -> Self

Creates a new Instruction::ElemDrop.

pub fn data_drop(index: impl Into<Data>) -> Self

Creates a new Instruction::DataDrop.

pub fn memory_size(result: impl Into<Reg>, memory: impl Into<Memory>) -> Self

Creates a new Instruction::MemorySize.

pub fn memory_grow(result: impl Into<Reg>, delta: impl Into<Reg>) -> Self

Creates a new Instruction::MemoryGrow.

pub fn memory_grow_by(result: impl Into<Reg>, delta: impl Into<u32>) -> Self

Creates a new Instruction::MemoryGrowBy.

pub fn memory_copy( dst: impl Into<Reg>, src: impl Into<Reg>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryCopy.

pub fn memory_copy_to( dst: impl Into<Const16<u64>>, src: impl Into<Reg>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryCopyTo.

pub fn memory_copy_from( dst: impl Into<Reg>, src: impl Into<Const16<u64>>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryCopyFrom.

pub fn memory_copy_from_to( dst: impl Into<Const16<u64>>, src: impl Into<Const16<u64>>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryCopyFromTo.

pub fn memory_copy_exact( dst: impl Into<Reg>, src: impl Into<Reg>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::MemoryCopyExact.

pub fn memory_copy_to_exact( dst: impl Into<Const16<u64>>, src: impl Into<Reg>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::MemoryCopyToExact.

pub fn memory_copy_from_exact( dst: impl Into<Reg>, src: impl Into<Const16<u64>>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::MemoryCopyFromExact.

pub fn memory_copy_from_to_exact( dst: impl Into<Const16<u64>>, src: impl Into<Const16<u64>>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::MemoryCopyFromToExact.

pub fn memory_fill( dst: impl Into<Reg>, value: impl Into<Reg>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryFill.

pub fn memory_fill_at( dst: impl Into<Const16<u64>>, value: impl Into<Reg>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryFillAt.

pub fn memory_fill_imm( dst: impl Into<Reg>, value: impl Into<u8>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryFillImm.

pub fn memory_fill_exact( dst: impl Into<Reg>, value: impl Into<Reg>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::MemoryFillExact.

pub fn memory_fill_at_imm( dst: impl Into<Const16<u64>>, value: impl Into<u8>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryFillAtImm.

pub fn memory_fill_at_exact( dst: impl Into<Const16<u64>>, value: impl Into<Reg>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::MemoryFillAtExact.

pub fn memory_fill_imm_exact( dst: impl Into<Reg>, value: impl Into<u8>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::MemoryFillImmExact.

pub fn memory_fill_at_imm_exact( dst: impl Into<Const16<u64>>, value: impl Into<u8>, len: impl Into<Const16<u64>>, ) -> Self

Creates a new Instruction::MemoryFillAtImmExact.

pub fn memory_init( dst: impl Into<Reg>, src: impl Into<Reg>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryInit.

pub fn memory_init_to( dst: impl Into<Const16<u64>>, src: impl Into<Reg>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryInitTo.

pub fn memory_init_from( dst: impl Into<Reg>, src: impl Into<Const16<u32>>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryInitFrom.

pub fn memory_init_from_to( dst: impl Into<Const16<u64>>, src: impl Into<Const16<u32>>, len: impl Into<Reg>, ) -> Self

Creates a new Instruction::MemoryInitFromTo.

pub fn memory_init_exact( dst: impl Into<Reg>, src: impl Into<Reg>, len: impl Into<Const16<u32>>, ) -> Self

Creates a new Instruction::MemoryInitExact.

pub fn memory_init_to_exact( dst: impl Into<Const16<u64>>, src: impl Into<Reg>, len: impl Into<Const16<u32>>, ) -> Self

Creates a new Instruction::MemoryInitToExact.

pub fn memory_init_from_exact( dst: impl Into<Reg>, src: impl Into<Const16<u32>>, len: impl Into<Const16<u32>>, ) -> Self

Creates a new Instruction::MemoryInitFromExact.

pub fn memory_init_from_to_exact( dst: impl Into<Const16<u64>>, src: impl Into<Const16<u32>>, len: impl Into<Const16<u32>>, ) -> Self

Creates a new Instruction::MemoryInitFromToExact.

pub fn table_index(index: impl Into<Table>) -> Self

Creates a new Instruction::TableIndex.

pub fn memory_index(index: impl Into<Memory>) -> Self

Creates a new Instruction::MemoryIndex.

pub fn data_index(index: impl Into<Data>) -> Self

Creates a new Instruction::DataIndex.

pub fn elem_index(index: impl Into<Elem>) -> Self

Creates a new Instruction::ElemIndex.

pub fn const32(value: impl Into<AnyConst32>) -> Self

Creates a new Instruction::Const32.

pub fn i64const32(value: impl Into<Const32<i64>>) -> Self

Creates a new Instruction::I64Const32.

pub fn f64const32(value: impl Into<Const32<f64>>) -> Self

Creates a new Instruction::F64Const32.

pub fn branch_table_target( results: impl Into<RegSpan>, offset: impl Into<BranchOffset>, ) -> Self

Creates a new Instruction::BranchTableTarget.

pub fn branch_table_target_non_overlapping( results: impl Into<RegSpan>, offset: impl Into<BranchOffset>, ) -> Self

Creates a new Instruction::BranchTableTargetNonOverlapping.

pub fn imm16_and_imm32( imm16: impl Into<AnyConst16>, imm32: impl Into<AnyConst32>, ) -> Self

Creates a new Instruction::Imm16AndImm32.

pub fn register_and_imm32( reg: impl Into<Reg>, imm: impl Into<AnyConst32>, ) -> Self

Creates a new Instruction::RegisterAndImm32.

pub fn register_span(span: impl Into<BoundedRegSpan>) -> Self

Creates a new Instruction::RegisterSpan.

pub fn register(reg: impl Into<Reg>) -> Self

Creates a new Instruction::Register.

pub fn register2(regs: impl Into<[Reg; 2]>) -> Self

Creates a new Instruction::Register2.

pub fn register3(regs: impl Into<[Reg; 3]>) -> Self

Creates a new Instruction::Register3.

pub fn register_list(regs: impl Into<[Reg; 3]>) -> Self

Creates a new Instruction::RegisterList.

pub fn call_indirect_params( index: impl Into<Reg>, table: impl Into<Table>, ) -> Self

Creates a new Instruction::CallIndirectParams.

pub fn call_indirect_params_imm16( index: impl Into<Const16<u64>>, table: impl Into<Table>, ) -> Self

Creates a new Instruction::CallIndirectParamsImm16.

impl Instruction

pub fn result(&self) -> Option<Reg>

Returns the result Reg for self.

Returns None if self does not statically return a single Reg.

impl Instruction

pub fn return_reg2_ext(reg0: impl Into<Reg>, reg1: impl Into<Reg>) -> Self

Creates a new Instruction::ReturnReg2 for the given Reg indices.

pub fn return_reg3_ext( reg0: impl Into<Reg>, reg1: impl Into<Reg>, reg2: impl Into<Reg>, ) -> Self

Creates a new Instruction::ReturnReg3 for the given Reg indices.

pub fn return_many_ext( reg0: impl Into<Reg>, reg1: impl Into<Reg>, reg2: impl Into<Reg>, ) -> Self

Creates a new Instruction::ReturnMany for the given Reg indices.

pub fn return_nez_reg2_ext( condition: impl Into<Reg>, value0: impl Into<Reg>, value1: impl Into<Reg>, ) -> Self

Creates a new Instruction::ReturnNezReg2 for the given condition and value.

pub fn return_nez_many_ext( condition: impl Into<Reg>, head0: impl Into<Reg>, head1: impl Into<Reg>, ) -> Self

Creates a new Instruction::ReturnNezMany for the given condition and value.

pub fn copy2_ext( results: RegSpan, value0: impl Into<Reg>, value1: impl Into<Reg>, ) -> Self

Creates a new Instruction::Copy2.

pub fn copy_many_ext( results: RegSpan, head0: impl Into<Reg>, head1: impl Into<Reg>, ) -> Self

Creates a new Instruction::CopyMany.

pub fn copy_many_non_overlapping_ext( results: RegSpan, head0: impl Into<Reg>, head1: impl Into<Reg>, ) -> Self

Creates a new Instruction::CopyManyNonOverlapping.

pub fn register2_ext(reg0: impl Into<Reg>, reg1: impl Into<Reg>) -> Self

Creates a new Instruction::Register2 instruction parameter.

pub fn register3_ext( reg0: impl Into<Reg>, reg1: impl Into<Reg>, reg2: impl Into<Reg>, ) -> Self

Creates a new Instruction::Register3 instruction parameter.

pub fn register_list_ext( reg0: impl Into<Reg>, reg1: impl Into<Reg>, reg2: impl Into<Reg>, ) -> Self

Creates a new Instruction::RegisterList instruction parameter.

pub fn register_and_offset_hi( reg: impl Into<Reg>, offset_hi: Offset64Hi, ) -> Self

Creates a new Instruction::RegisterAndImm32 from the given reg and offset_hi.

pub fn filter_register_and_offset_hi(self) -> Result<(Reg, Offset64Hi), Self>

Returns Some Reg and Offset64Hi if encoded properly.

Errors

Returns back self if it was an incorrect Instruction. This allows for a better error message to inform the user.

pub fn imm16_and_offset_hi( value: impl Into<AnyConst16>, offset_hi: Offset64Hi, ) -> Self

Creates a new Instruction::Imm16AndImm32 from the given value and offset_hi.

pub fn filter_imm16_and_offset_hi<T>(self) -> Result<(T, Offset64Hi), Self>

where T: From<AnyConst16>,

Returns Some Reg and Offset64Hi if encoded properly.

Errors

Returns back self if it was an incorrect Instruction. This allows for a better error message to inform the user.

impl Instruction

pub fn visit_regs<V: VisitRegs>(&mut self, visitor: &mut V)

Visit Regs of self via the visitor.

Trait Implementations

impl Clone for Instruction

fn clone(&self) -> Instruction

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Instruction

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for Instruction

fn eq(&self, other: &Instruction) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Instruction

impl Eq for Instruction

impl StructuralPartialEq for Instruction