pub struct CacheParameter { /* private fields */ }
Expand description

Information about an individual cache in the hierarchy.

Platforms

❌ AMD ✅ Intel

Implementations

Cache Type

Cache Level (starts at 1)

Self Initializing cache level (does not need SW initialization).

Fully Associative cache

Maximum number of addressable IDs for logical processors sharing this cache

Maximum number of addressable IDs for processor cores in the physical package

System Coherency Line Size (Bits 11-00)

Physical Line partitions (Bits 21-12)

Ways of associativity (Bits 31-22)

Number of Sets (Bits 31-00)

Write-Back Invalidate/Invalidate (Bit 0) False: WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this cache. True: WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing this cache.

Cache Inclusiveness (Bit 1) False: Cache is not inclusive of lower cache levels. True: Cache is inclusive of lower cache levels.

Complex Cache Indexing (Bit 2) False: Direct mapped cache. True: A complex function is used to index the cache, potentially using all address bits.

Trait Implementations

Returns a copy of the value. Read more

Performs copy-assignment from source. Read more

Formats the value using the given formatter. Read more

This method tests for self and other values to be equal, and is used by ==. Read more

This method tests for !=.

Auto Trait Implementations

Blanket Implementations

Gets the TypeId of self. Read more

Immutably borrows from an owned value. Read more

Mutably borrows from an owned value. Read more

Returns the argument unchanged.

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

The type returned in the event of a conversion error.

Performs the conversion.

The type returned in the event of a conversion error.

Performs the conversion.