Struct OpCodeInfo

pub struct OpCodeInfo { /* private fields */ }

Opcode info, returned by Code::op_code() and Instruction::op_code()

Implementations

impl OpCodeInfo

pub const fn code(&self) -> Code

Gets the code

Examples

use iced_x86::*;

let op_code = Code::EVEX_Vmovapd_ymm_k1z_ymmm256.op_code();
assert_eq!(op_code.code(), Code::EVEX_Vmovapd_ymm_k1z_ymmm256);

pub fn mnemonic(&self) -> Mnemonic

Gets the mnemonic

Examples

use iced_x86::*;

let op_code = Code::EVEX_Vmovapd_ymm_k1z_ymmm256.op_code();
assert_eq!(op_code.mnemonic(), Mnemonic::Vmovapd);

pub const fn encoding(&self) -> EncodingKind

Gets the encoding

Examples

use iced_x86::*;

let op_code = Code::EVEX_Vmovapd_ymm_k1z_ymmm256.op_code();
assert_eq!(op_code.encoding(), EncodingKind::EVEX);

pub fn is_instruction(&self) -> bool

true if it’s an instruction, false if it’s eg. Code::INVALID, db, dw, dd, dq, zero_bytes

Examples

use iced_x86::*;

assert!(Code::EVEX_Vmovapd_ymm_k1z_ymmm256.op_code().is_instruction());
assert!(!Code::INVALID.op_code().is_instruction());
assert!(!Code::DeclareByte.op_code().is_instruction());

pub const fn mode16(&self) -> bool

true if it’s an instruction available in 16-bit mode

pub const fn mode32(&self) -> bool

true if it’s an instruction available in 32-bit mode

pub const fn mode64(&self) -> bool

true if it’s an instruction available in 64-bit mode

pub const fn fwait(&self) -> bool

true if an FWAIT (9B) instruction is added before the instruction

pub const fn operand_size(&self) -> u32

(Legacy encoding) Gets the required operand size (16,32,64) or 0

pub const fn address_size(&self) -> u32

(Legacy encoding) Gets the required address size (16,32,64) or 0

pub const fn l(&self) -> u32

(VEX/XOP/EVEX) L / L'L value or default value if is_lig() is true

pub const fn w(&self) -> u32

(VEX/XOP/EVEX/MVEX) W value or default value if is_wig() or is_wig32() is true

pub const fn is_lig(&self) -> bool

(VEX/XOP/EVEX) true if the L / L'L fields are ignored.

EVEX: if reg-only ops and {er} (EVEX.b is set), L'L is the rounding control and not ignored.

pub const fn is_wig(&self) -> bool

(VEX/XOP/EVEX/MVEX) true if the W field is ignored in 16/32/64-bit modes

pub const fn is_wig32(&self) -> bool

(VEX/XOP/EVEX/MVEX) true if the W field is ignored in 16/32-bit modes (but not 64-bit mode)

pub const fn tuple_type(&self) -> TupleType

(EVEX/MVEX) Gets the tuple type

pub fn mvex_eh_bit(&self) -> MvexEHBit

(MVEX) Gets the EH bit that’s required to encode this instruction

pub fn mvex_can_use_eviction_hint(&self) -> bool

(MVEX) true if the instruction supports eviction hint (if it has a memory operand)

pub fn mvex_can_use_imm_rounding_control(&self) -> bool

(MVEX) true if the instruction’s rounding control bits are stored in imm8[1:0]

pub fn mvex_ignores_op_mask_register(&self) -> bool

(MVEX) true if the instruction ignores op mask registers (eg. {k1})

pub fn mvex_no_sae_rc(&self) -> bool

(MVEX) true if the instruction must have MVEX.SSS=000 if MVEX.EH=1

pub fn mvex_tuple_type_lut_kind(&self) -> MvexTupleTypeLutKind

(MVEX) Gets the tuple type / conv lut kind

pub fn mvex_conversion_func(&self) -> MvexConvFn

(MVEX) Gets the conversion function, eg. Sf32

pub fn mvex_valid_conversion_funcs_mask(&self) -> u8

(MVEX) Gets flags indicating which conversion functions are valid (bit 0 == func 0)

pub fn mvex_valid_swizzle_funcs_mask(&self) -> u8

(MVEX) Gets flags indicating which swizzle functions are valid (bit 0 == func 0)

pub fn memory_size(&self) -> MemorySize

If it has a memory operand, gets the MemorySize (non-broadcast memory type)

pub fn broadcast_memory_size(&self) -> MemorySize

If it has a memory operand, gets the MemorySize (broadcast memory type)

pub const fn can_broadcast(&self) -> bool

(EVEX) true if the instruction supports broadcasting (EVEX.b bit) (if it has a memory operand)

pub const fn can_use_rounding_control(&self) -> bool

(EVEX/MVEX) true if the instruction supports rounding control

pub const fn can_suppress_all_exceptions(&self) -> bool

(EVEX/MVEX) true if the instruction supports suppress all exceptions

pub const fn can_use_op_mask_register(&self) -> bool

(EVEX/MVEX) true if an opmask register can be used

pub const fn require_op_mask_register(&self) -> bool

(EVEX/MVEX) true if a non-zero opmask register must be used

pub const fn can_use_zeroing_masking(&self) -> bool

(EVEX) true if the instruction supports zeroing masking (if one of the opmask registers K1-K7 is used and destination operand is not a memory operand)

pub const fn can_use_lock_prefix(&self) -> bool

true if the LOCK (F0) prefix can be used

pub const fn can_use_xacquire_prefix(&self) -> bool

true if the XACQUIRE (F2) prefix can be used

pub const fn can_use_xrelease_prefix(&self) -> bool

true if the XRELEASE (F3) prefix can be used

pub const fn can_use_rep_prefix(&self) -> bool

true if the REP / REPE (F3) prefixes can be used

pub const fn can_use_repne_prefix(&self) -> bool

true if the REPNE (F2) prefix can be used

pub const fn can_use_bnd_prefix(&self) -> bool

true if the BND (F2) prefix can be used

pub const fn can_use_hint_taken_prefix(&self) -> bool

true if the HINT-TAKEN (3E) and HINT-NOT-TAKEN (2E) prefixes can be used

pub const fn can_use_notrack_prefix(&self) -> bool

true if the NOTRACK (3E) prefix can be used

pub const fn ignores_rounding_control(&self) -> bool

true if rounding control is ignored (#UD is not generated)

pub const fn amd_lock_reg_bit(&self) -> bool

true if the LOCK prefix can be used as an extra register bit (bit 3) to access registers 8-15 without a REX prefix (eg. in 32-bit mode)

pub const fn default_op_size64(&self) -> bool

true if the default operand size is 64 in 64-bit mode. A 66 prefix can switch to 16-bit operand size.

pub const fn force_op_size64(&self) -> bool

true if the operand size is always 64 in 64-bit mode. A 66 prefix is ignored.

pub const fn intel_force_op_size64(&self) -> bool

true if the Intel decoder forces 64-bit operand size. A 66 prefix is ignored.

pub const fn must_be_cpl0(&self) -> bool

true if it can only be executed when CPL=0

pub const fn cpl0(&self) -> bool

true if it can be executed when CPL=0

pub const fn cpl1(&self) -> bool

true if it can be executed when CPL=1

pub const fn cpl2(&self) -> bool

true if it can be executed when CPL=2

pub const fn cpl3(&self) -> bool

true if it can be executed when CPL=3

pub const fn is_input_output(&self) -> bool

true if the instruction accesses the I/O address space (eg. IN, OUT, INS, OUTS)

pub const fn is_nop(&self) -> bool

true if it’s one of the many nop instructions (does not include FPU nop instructions, eg. FNOP)

pub const fn is_reserved_nop(&self) -> bool

true if it’s one of the many reserved nop instructions (eg. 0F0D, 0F18-0F1F)

pub const fn is_serializing_intel(&self) -> bool

true if it’s a serializing instruction (Intel CPUs)

pub const fn is_serializing_amd(&self) -> bool

true if it’s a serializing instruction (AMD CPUs)

pub const fn may_require_cpl0(&self) -> bool

true if the instruction requires either CPL=0 or CPL<=3 depending on some CPU option (eg. CR4.TSD, CR4.PCE, CR4.UMIP)

pub const fn is_cet_tracked(&self) -> bool

true if it’s a tracked JMP/CALL indirect instruction (CET)

pub const fn is_non_temporal(&self) -> bool

true if it’s a non-temporal hint memory access (eg. MOVNTDQ)

pub const fn is_fpu_no_wait(&self) -> bool

true if it’s a no-wait FPU instruction, eg. FNINIT

pub const fn ignores_mod_bits(&self) -> bool

true if the mod bits are ignored and it’s assumed modrm[7:6] == 11b

pub const fn no66(&self) -> bool

true if the 66 prefix is not allowed (it will #UD)

pub const fn nfx(&self) -> bool

true if the F2/F3 prefixes aren’t allowed

pub const fn requires_unique_reg_nums(&self) -> bool

true if the index reg’s reg-num (vsib op) (if any) and register ops’ reg-nums must be unique, eg. MNEMONIC XMM1,YMM1,[RAX+ZMM1*2] is invalid. Registers = XMM/YMM/ZMM/TMM.

pub const fn requires_unique_dest_reg_num(&self) -> bool

true if the destination register’s reg-num must not be present in any other operand, eg. MNEMONIC XMM1,YMM1,[RAX+ZMM1*2] is invalid. Registers = XMM/YMM/ZMM/TMM.

pub const fn is_privileged(&self) -> bool

true if it’s a privileged instruction (all CPL=0 instructions (except VMCALL) and IOPL instructions IN, INS, OUT, OUTS, CLI, STI)

pub const fn is_save_restore(&self) -> bool

true if it reads/writes too many registers

pub const fn is_stack_instruction(&self) -> bool

true if it’s an instruction that implicitly uses the stack register, eg. CALL, POP, etc

pub const fn ignores_segment(&self) -> bool

true if the instruction doesn’t read the segment register if it uses a memory operand

pub const fn is_op_mask_read_write(&self) -> bool

true if the opmask register is read and written (instead of just read). This also implies that it can’t be K0.

pub const fn real_mode(&self) -> bool

true if it can be executed in real mode

pub const fn protected_mode(&self) -> bool

true if it can be executed in protected mode

pub const fn virtual8086_mode(&self) -> bool

true if it can be executed in virtual 8086 mode

pub const fn compatibility_mode(&self) -> bool

true if it can be executed in compatibility mode

pub const fn long_mode(&self) -> bool

true if it can be executed in 64-bit mode

pub const fn use_outside_smm(&self) -> bool

true if it can be used outside SMM

pub const fn use_in_smm(&self) -> bool

true if it can be used in SMM

pub const fn use_outside_enclave_sgx(&self) -> bool

true if it can be used outside an enclave (SGX)

pub const fn use_in_enclave_sgx1(&self) -> bool

true if it can be used inside an enclave (SGX1)

pub const fn use_in_enclave_sgx2(&self) -> bool

true if it can be used inside an enclave (SGX2)

pub const fn use_outside_vmx_op(&self) -> bool

true if it can be used outside VMX operation

pub const fn use_in_vmx_root_op(&self) -> bool

true if it can be used in VMX root operation

pub const fn use_in_vmx_non_root_op(&self) -> bool

true if it can be used in VMX non-root operation

pub const fn use_outside_seam(&self) -> bool

true if it can be used outside SEAM

pub const fn use_in_seam(&self) -> bool

true if it can be used in SEAM

pub const fn tdx_non_root_gen_ud(&self) -> bool

true if #UD is generated in TDX non-root operation

pub const fn tdx_non_root_gen_ve(&self) -> bool

true if #VE is generated in TDX non-root operation

pub const fn tdx_non_root_may_gen_ex(&self) -> bool

true if an exception (eg. #GP(0), #VE) may be generated in TDX non-root operation

pub const fn intel_vm_exit(&self) -> bool

(Intel VMX) true if it causes a VM exit in VMX non-root operation

pub const fn intel_may_vm_exit(&self) -> bool

(Intel VMX) true if it may cause a VM exit in VMX non-root operation

pub const fn intel_smm_vm_exit(&self) -> bool

(Intel VMX) true if it causes an SMM VM exit in VMX root operation (if dual-monitor treatment is activated)

pub const fn amd_vm_exit(&self) -> bool

(AMD SVM) true if it causes a #VMEXIT in guest mode

pub const fn amd_may_vm_exit(&self) -> bool

(AMD SVM) true if it may cause a #VMEXIT in guest mode

pub const fn tsx_abort(&self) -> bool

true if it causes a TSX abort inside a TSX transaction

pub const fn tsx_impl_abort(&self) -> bool

true if it causes a TSX abort inside a TSX transaction depending on the implementation

pub const fn tsx_may_abort(&self) -> bool

true if it may cause a TSX abort inside a TSX transaction depending on some condition

pub const fn intel_decoder16(&self) -> bool

true if it’s decoded by iced’s 16-bit Intel decoder

pub const fn intel_decoder32(&self) -> bool

true if it’s decoded by iced’s 32-bit Intel decoder

pub const fn intel_decoder64(&self) -> bool

true if it’s decoded by iced’s 64-bit Intel decoder

pub const fn amd_decoder16(&self) -> bool

true if it’s decoded by iced’s 16-bit AMD decoder

pub const fn amd_decoder32(&self) -> bool

true if it’s decoded by iced’s 32-bit AMD decoder

pub const fn amd_decoder64(&self) -> bool

true if it’s decoded by iced’s 64-bit AMD decoder

pub fn decoder_option(&self) -> u32

Gets the decoder option that’s needed to decode the instruction or DecoderOptions::NONE. The return value is a DecoderOptions value.

pub const fn table(&self) -> OpCodeTableKind

Gets the opcode table

pub const fn mandatory_prefix(&self) -> MandatoryPrefix

Gets the mandatory prefix

pub const fn op_code(&self) -> u32

Gets the opcode byte(s). The low byte(s) of this value is the opcode. The length is in op_code_len(). It doesn’t include the table value, see table().

Examples

use iced_x86::*;

assert_eq!(Code::Ffreep_sti.op_code().op_code(), 0xDFC0);
assert_eq!(Code::Vmrunw.op_code().op_code(), 0x01D8);
assert_eq!(Code::Sub_r8_rm8.op_code().op_code(), 0x2A);
assert_eq!(Code::Cvtpi2ps_xmm_mmm64.op_code().op_code(), 0x2A);

pub const fn op_code_len(&self) -> u32

Gets the length of the opcode bytes (op_code()). The low bytes is the opcode value.

Examples

use iced_x86::*;

assert_eq!(Code::Ffreep_sti.op_code().op_code_len(), 2);
assert_eq!(Code::Vmrunw.op_code().op_code_len(), 2);
assert_eq!(Code::Sub_r8_rm8.op_code().op_code_len(), 1);
assert_eq!(Code::Cvtpi2ps_xmm_mmm64.op_code().op_code_len(), 1);

pub const fn is_group(&self) -> bool

true if it’s part of a group

pub const fn group_index(&self) -> i32

Group index (0-7) or -1. If it’s 0-7, it’s stored in the reg field of the modrm byte.

pub const fn is_rm_group(&self) -> bool

true if it’s part of a modrm.rm group

pub const fn rm_group_index(&self) -> i32

Group index (0-7) or -1. If it’s 0-7, it’s stored in the rm field of the modrm byte.

pub fn op_count(&self) -> u32

Gets the number of operands

pub const fn op0_kind(&self) -> OpCodeOperandKind

Gets operand #0’s opkind

pub const fn op1_kind(&self) -> OpCodeOperandKind

Gets operand #1’s opkind

pub const fn op2_kind(&self) -> OpCodeOperandKind

Gets operand #2’s opkind

pub const fn op3_kind(&self) -> OpCodeOperandKind

Gets operand #3’s opkind

pub const fn op4_kind(&self) -> OpCodeOperandKind

Gets operand #4’s opkind

pub fn op_kind(&self, operand: u32) -> OpCodeOperandKind

Gets an operand’s opkind

Arguments

• operand: Operand number, 0-4

pub fn op_kinds(&self) -> &[OpCodeOperandKind]

Gets all operand kinds

pub const fn is_available_in_mode(&self, bitness: u32) -> bool

Checks if the instruction is available in 16-bit mode, 32-bit mode or 64-bit mode

Arguments

• bitness: 16, 32 or 64

pub fn op_code_string(&self) -> &str

Gets the opcode string, eg. VEX.128.66.0F38.W0 78 /r, see also instruction_string()

Examples

use iced_x86::*;

let op_code = Code::EVEX_Vmovapd_ymm_k1z_ymmm256.op_code();
assert_eq!(op_code.op_code_string(), "EVEX.256.66.0F.W1 28 /r");

pub fn instruction_string(&self) -> &str

Gets the instruction string, eg. VPBROADCASTB xmm1, xmm2/m8, see also op_code_string()

Examples

use iced_x86::*;

let op_code = Code::EVEX_Vmovapd_ymm_k1z_ymmm256.op_code();
assert_eq!(op_code.instruction_string(), "VMOVAPD ymm1 {k1}{z}, ymm2/m256");

Trait Implementations

impl Clone for OpCodeInfo

fn clone(&self) -> OpCodeInfo

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for OpCodeInfo

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Display for OpCodeInfo

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.