Expand description
All the interface bits for RISC-V.
Modules§
- Debug Module Communication
- Debug sequences to operate special requirements RISC-V targets.
Structs§
- Abstract Control and Status (see 3.12.6) A
bitfield::bitfield!
register mapping for the registerabstractcs
located at address0x16
. dmcontrol
register, located at address 0x10 Abitfield::bitfield!
register mapping for the registerdmcontrol
located at address0x10
.- Readonly
dmstatus
register. - Hart Info (see 3.12.3) A
bitfield::bitfield!
register mapping for the registerhartinfo
located at address0x12
. - Isa and Extensions (see RISC-V Privileged Spec, 3.1.1) A
bitfield::bitfield!
register mapping for the registermisa
located at address0x301
. - An interface to operate a RISC-V core.
- Flags used to control the
SpecificCoreState
for RiscV architecture
Constants§
- The program counter register.