pub struct ThermalPowerInfo { /* private fields */ }

Implementations§

Number of Interrupt Thresholds in Digital Thermal Sensor

Digital temperature sensor is supported if set.

Intel Turbo Boost Technology Available (see description of IA32_MISC_ENABLE[38]).

ARAT. APIC-Timer-always-running feature is supported if set.

PLN. Power limit notification controls are supported if set.

ECMD. Clock modulation duty cycle extension is supported if set.

PTM. Package thermal management is supported if set.

HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.

HWP Notification. IA32_HWP_INTERRUPT MSR is supported if set.

HWP Activity Window. IA32_HWP_REQUEST[bits 41:32] is supported if set.

HWP Energy Performance Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set.

HWP Package Level Request. IA32_HWP_REQUEST_PKG MSR is supported if set.

HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are supported if set.

Intel® Turbo Boost Max Technology 3.0 available.

HWP Capabilities. Highest Performance change is supported if set.

HWP PECI override is supported if set.

Flexible HWP is supported if set.

Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.

Ignoring Idle Logical Processor HWP request is supported if set.

Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF). The capability to provide a measure of delivered processor performance (since last reset of the counters), as a percentage of expected processor performance at frequency specified in CPUID Brand String Bits 02 - 01

The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H)

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