Struct MIMXRT5xxS

pub struct MIMXRT5xxS { /* private fields */ }

Debug sequences for MIMXRT5xxS MCUs.

MCUs in this series do not have any on-board flash memory, and instead there is a non-programmable boot ROM which attempts to find a suitable program from a variety of different sources. The entry point for application code therefore varies depending on the boot medium.

Note: These sequences assume that the chip’s PIO4_5 is connected to an active-low reset signal on the NOR flash chip, and will attempt to reset the flash when resetting the overall system. This pin selection matches the evaluation kit (MIMXRT595-EVK) but there’s currently no way to make that customizable for other boards.

Because the system begins execution in the boot ROM, it isn’t possible to use a standard reset vector catch on this platform. Instead, the series datasheet (section 60.3.4) describes the following protocol:

• Set a data watchpoint for a read from location 0x50002034.
• Use SYSRESETREQ to reset the core and peripherals.
• Wait 100ms to allow the boot ROM to re-enable debug.
• Check whether the core is halted due to the watchpoint, by checking DHCSR.
• If the core doesn’t halt or halts for some reason other than the watchpoint, use the special debug mailbox protocol to exit the ISP mode and enter an infinite loop, at which point we can halt the MCU explicitly.
• Clear the data watchpoint.

The debug mailbox protocol handles, among other things, recovering debug access when the part enters its ISP mode. ISP mode has debug disabled to prevent tampering with the system’s security features. Datasheet section 60.3.1 describes the special debug recovery process.

Implementations

impl MIMXRT5xxS

pub fn create(family: MIMXRTFamily) -> Arc<dyn ArmDebugSequence>

Create a sequence handle for the MIMXRT5xxS.

Trait Implementations

impl ArmDebugSequence for MIMXRT5xxS

fn debug_port_start( &self, interface: &mut ArmCommunicationInterface<Initialized>, dp: DpAddress, ) -> Result<(), ArmError>

Connect to the target debug port and power it up. This is based on the DebugPortStart function from the ARM SVD Debug Description.

fn reset_system( &self, probe: &mut dyn ArmMemoryInterface, core_type: CoreType, _debug_base: Option<u64>, ) -> Result<(), ArmError>

Executes a system-wide reset without debug domain (or warm-reset that preserves debug connection) via software mechanisms, for example AIRCR.SYSRESETREQ. This is based on the ResetSystem function from the ARM SVD Debug Description.

fn reset_hardware_deassert( &self, memory: &mut dyn ArmMemoryInterface, ) -> Result<(), ArmError>

De-Assert a system-wide reset line nRST. This is based on the ResetHardwareDeassert function from the ARM SVD Debug Description.

fn reset_hardware_assert( &self, interface: &mut dyn DapProbe, ) -> Result<(), ArmError>

Assert a system-wide reset line nRST. This is based on the ResetHardwareAssert function from the ARM SVD Debug Description.

fn debug_port_setup( &self, interface: &mut dyn DapProbe, dp: DpAddress, ) -> Result<(), ArmError>

Prepare the target debug port for connection. This is based on the DebugPortSetup function from the ARM SVD Debug Description.

fn debug_core_start( &self, interface: &mut dyn ArmProbeInterface, core_ap: &FullyQualifiedApAddress, core_type: CoreType, debug_base: Option<u64>, cti_base: Option<u64>, ) -> Result<(), ArmError>

Initialize core debug system. This is based on the DebugCoreStart function from the ARM SVD Debug Description.

fn reset_catch_set( &self, core: &mut dyn ArmMemoryInterface, core_type: CoreType, debug_base: Option<u64>, ) -> Result<(), ArmError>

Configure the target to stop code execution after a reset. After this, the core will halt when it comes out of reset. This is based on the ResetCatchSet function from the ARM SVD Debug Description.

fn reset_catch_clear( &self, core: &mut dyn ArmMemoryInterface, core_type: CoreType, debug_base: Option<u64>, ) -> Result<(), ArmError>

Free hardware resources allocated by ResetCatchSet. This is based on the ResetCatchSet function from the ARM SVD Debug Description.

fn trace_start( &self, interface: &mut dyn ArmProbeInterface, components: &[CoresightComponent], _sink: &TraceSink, ) -> Result<(), ArmError>

Enable target trace capture.

fn debug_device_unlock( &self, _interface: &mut dyn ArmProbeInterface, _default_ap: &FullyQualifiedApAddress, _permissions: &Permissions, ) -> Result<(), ArmError>

Check if the device is in a locked state and unlock it. Use query command elements for user confirmation. Executed after having powered up the debug port. This is based on the DebugDeviceUnlock function from the ARM SVD Debug Description.

fn recover_support_start( &self, _interface: &mut dyn ArmMemoryInterface, ) -> Result<(), ArmError>

Executed before step or run command to support recovery from a lost target connection, e.g. after a low power mode. This is based on the RecoverSupportStart function from the ARM SVD Debug Description.

fn debug_core_stop( &self, interface: &mut dyn ArmMemoryInterface, core_type: CoreType, ) -> Result<(), ArmError>

Executed when the debugger session is disconnected from the core.

fn debug_port_stop( &self, interface: &mut dyn DapProbe, dp: DpAddress, ) -> Result<(), ArmError>

Sequence executed when disconnecting from a debug port.

fn debug_port_connect( &self, interface: &mut dyn DapProbe, dp: DpAddress, ) -> Result<(), ArmError>

Perform a SWD line reset or enter the JTAG Run-Test-Idle state, and then try to connect to a debug port.

fn prepare_running_on_ram( &self, vector_table_addr: u64, session: &mut Session, ) -> Result<(), Error>

This ARM sequence is called if an image was flashed to RAM directly. It will perform the necessary preparation to run that image.

fn debug_erase_sequence(&self) -> Option<Arc<dyn DebugEraseSequence>>

Return the Debug Erase Sequence implementation if it exists

fn allowed_access_ports(&self) -> Vec<u8>

Return the APs that are expected to work.

impl Debug for MIMXRT5xxS

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.