probe_rs::architecture::arm::sequences

Trait ArmDebugSequence

Source 
pub trait ArmDebugSequence:
    Send
    + Sync
    + Debug {

Show 17 methods    // Provided methods
    fn reset_hardware_assert(
        &self,
        interface: &mut dyn DapProbe,
    ) -> Result<(), ArmError> { ... }
    fn reset_hardware_deassert(
        &self,
        memory: &mut dyn ArmMemoryInterface,
    ) -> Result<(), ArmError> { ... }
    fn debug_port_setup(
        &self,
        interface: &mut dyn DapProbe,
        dp: DpAddress,
    ) -> Result<(), ArmError> { ... }
    fn debug_port_start(
        &self,
        interface: &mut ArmCommunicationInterface<Initialized>,
        dp: DpAddress,
    ) -> Result<(), ArmError> { ... }
    fn debug_core_start(
        &self,
        interface: &mut dyn ArmProbeInterface,
        core_ap: &FullyQualifiedApAddress,
        core_type: CoreType,
        debug_base: Option<u64>,
        cti_base: Option<u64>,
    ) -> Result<(), ArmError> { ... }
    fn reset_catch_set(
        &self,
        core: &mut dyn ArmMemoryInterface,
        core_type: CoreType,
        debug_base: Option<u64>,
    ) -> Result<(), ArmError> { ... }
    fn reset_catch_clear(
        &self,
        core: &mut dyn ArmMemoryInterface,
        core_type: CoreType,
        debug_base: Option<u64>,
    ) -> Result<(), ArmError> { ... }
    fn trace_start(
        &self,
        interface: &mut dyn ArmProbeInterface,
        components: &[CoresightComponent],
        _sink: &TraceSink,
    ) -> Result<(), ArmError> { ... }
    fn reset_system(
        &self,
        interface: &mut dyn ArmMemoryInterface,
        core_type: CoreType,
        debug_base: Option<u64>,
    ) -> Result<(), ArmError> { ... }
    fn debug_device_unlock(
        &self,
        _interface: &mut dyn ArmProbeInterface,
        _default_ap: &FullyQualifiedApAddress,
        _permissions: &Permissions,
    ) -> Result<(), ArmError> { ... }
    fn recover_support_start(
        &self,
        _interface: &mut dyn ArmMemoryInterface,
    ) -> Result<(), ArmError> { ... }
    fn debug_core_stop(
        &self,
        interface: &mut dyn ArmMemoryInterface,
        core_type: CoreType,
    ) -> Result<(), ArmError> { ... }
    fn debug_port_stop(
        &self,
        interface: &mut dyn DapProbe,
        dp: DpAddress,
    ) -> Result<(), ArmError> { ... }
    fn debug_port_connect(
        &self,
        interface: &mut dyn DapProbe,
        dp: DpAddress,
    ) -> Result<(), ArmError> { ... }
    fn prepare_running_on_ram(
        &self,
        vector_table_addr: u64,
        session: &mut Session,
    ) -> Result<(), Error> { ... }
    fn debug_erase_sequence(&self) -> Option<Arc<dyn DebugEraseSequence>> { ... }
    fn allowed_access_ports(&self) -> Vec<u8> { ... }

}
Expand description

A interface to operate debug sequences for ARM targets.

Should be implemented on a custom handle for chips that require special sequence code.

Provided Methods§

Source

fn reset_hardware_assert( &self, interface: &mut dyn DapProbe, ) -> Result<(), ArmError>

Assert a system-wide reset line nRST. This is based on the ResetHardwareAssert function from the ARM SVD Debug Description.

Source

fn reset_hardware_deassert( &self, memory: &mut dyn ArmMemoryInterface, ) -> Result<(), ArmError>

De-Assert a system-wide reset line nRST. This is based on the ResetHardwareDeassert function from the ARM SVD Debug Description.

Source

fn debug_port_setup( &self, interface: &mut dyn DapProbe, dp: DpAddress, ) -> Result<(), ArmError>

Prepare the target debug port for connection. This is based on the DebugPortSetup function from the ARM SVD Debug Description.

After this function has been executed, it should be possible to read and write registers using SWD requests.

If this function cannot read the DPIDR register, it will retry up to 5 times, and return an error if it still cannot read it.

Source

fn debug_port_start( &self, interface: &mut ArmCommunicationInterface<Initialized>, dp: DpAddress, ) -> Result<(), ArmError>

Connect to the target debug port and power it up. This is based on the DebugPortStart function from the ARM SVD Debug Description.

Source

fn debug_core_start( &self, interface: &mut dyn ArmProbeInterface, core_ap: &FullyQualifiedApAddress, core_type: CoreType, debug_base: Option<u64>, cti_base: Option<u64>, ) -> Result<(), ArmError>

Initialize core debug system. This is based on the DebugCoreStart function from the ARM SVD Debug Description.

Source

fn reset_catch_set( &self, core: &mut dyn ArmMemoryInterface, core_type: CoreType, debug_base: Option<u64>, ) -> Result<(), ArmError>

Configure the target to stop code execution after a reset. After this, the core will halt when it comes out of reset. This is based on the ResetCatchSet function from the ARM SVD Debug Description.

Source

fn reset_catch_clear( &self, core: &mut dyn ArmMemoryInterface, core_type: CoreType, debug_base: Option<u64>, ) -> Result<(), ArmError>

Free hardware resources allocated by ResetCatchSet. This is based on the ResetCatchSet function from the ARM SVD Debug Description.

Source

fn trace_start( &self, interface: &mut dyn ArmProbeInterface, components: &[CoresightComponent], _sink: &TraceSink, ) -> Result<(), ArmError>

Enable target trace capture.

§Note

This function is responsible for configuring any of the CoreSight link components, such as trace funnels, to route trace data to the specified trace sink.

This is based on the TraceStart function from the ARM SVD Debug Description.

Source

fn reset_system( &self, interface: &mut dyn ArmMemoryInterface, core_type: CoreType, debug_base: Option<u64>, ) -> Result<(), ArmError>

Executes a system-wide reset without debug domain (or warm-reset that preserves debug connection) via software mechanisms, for example AIRCR.SYSRESETREQ. This is based on the ResetSystem function from the ARM SVD Debug Description.

Source

fn debug_device_unlock( &self, _interface: &mut dyn ArmProbeInterface, _default_ap: &FullyQualifiedApAddress, _permissions: &Permissions, ) -> Result<(), ArmError>

Check if the device is in a locked state and unlock it. Use query command elements for user confirmation. Executed after having powered up the debug port. This is based on the DebugDeviceUnlock function from the ARM SVD Debug Description.

Source

fn recover_support_start( &self, _interface: &mut dyn ArmMemoryInterface, ) -> Result<(), ArmError>

Executed before step or run command to support recovery from a lost target connection, e.g. after a low power mode. This is based on the RecoverSupportStart function from the ARM SVD Debug Description.

Source

fn debug_core_stop( &self, interface: &mut dyn ArmMemoryInterface, core_type: CoreType, ) -> Result<(), ArmError>

Executed when the debugger session is disconnected from the core.

This is based on the DebugCoreStop function from the ARM SVD Debug Description.

Source

fn debug_port_stop( &self, interface: &mut dyn DapProbe, dp: DpAddress, ) -> Result<(), ArmError>

Sequence executed when disconnecting from a debug port.

Based on the DebugPortStop function from the ARM SVD Debug Description.

Source

fn debug_port_connect( &self, interface: &mut dyn DapProbe, dp: DpAddress, ) -> Result<(), ArmError>

Perform a SWD line reset or enter the JTAG Run-Test-Idle state, and then try to connect to a debug port.

This is executed as part of the standard debug_port_setup sequence, and when switching between debug ports in a SWD multi-drop configuration.

If the dp parameter is DpAddress::Default, a read of the DPIDR register will be performed after the line reset.

If the dp parameter is DpAddress::Multidrop, a write of the TARGETSEL register is done after the line reset, followed by a read of the DPIDR register.

This is not based on a sequence from the Open-CMSIS-Pack standard.

Source

fn prepare_running_on_ram( &self, vector_table_addr: u64, session: &mut Session, ) -> Result<(), Error>

This ARM sequence is called if an image was flashed to RAM directly. It will perform the necessary preparation to run that image.

Core should be already reset_and_halted right before this call.

Source

fn debug_erase_sequence(&self) -> Option<Arc<dyn DebugEraseSequence>>

Return the Debug Erase Sequence implementation if it exists

Source

fn allowed_access_ports(&self) -> Vec<u8>

Return the APs that are expected to work.

Implementors§