probe_rs::architecture::riscv::sequences

Trait RiscvDebugSequence

Source 
pub trait RiscvDebugSequence:
    Send
    + Sync
    + Debug {
    // Provided methods
    fn on_connect(
        &self,
        _interface: &mut RiscvCommunicationInterface<'_>,
    ) -> Result<(), Error> { ... }
    fn detect_flash_size(
        &self,
        _session: &mut Session,
    ) -> Result<Option<usize>, Error> { ... }
    fn reset_catch_set(
        &self,
        interface: &mut RiscvCommunicationInterface<'_>,
    ) -> Result<(), RiscvError> { ... }
    fn reset_catch_clear(
        &self,
        interface: &mut RiscvCommunicationInterface<'_>,
    ) -> Result<(), RiscvError> { ... }
    fn reset_system_and_halt(
        &self,
        interface: &mut RiscvCommunicationInterface<'_>,
        timeout: Duration,
    ) -> Result<(), Error> { ... }
}
Expand description

A interface to operate debug sequences for RISC-V targets.

Should be implemented on a custom handle for chips that require special sequence code.

Provided Methods§

Source

fn on_connect( &self, _interface: &mut RiscvCommunicationInterface<'_>, ) -> Result<(), Error>

Executed when the probe establishes a connection to the target.

Source

fn detect_flash_size( &self, _session: &mut Session, ) -> Result<Option<usize>, Error>

Detects the flash size of the target.

Source

fn reset_catch_set( &self, interface: &mut RiscvCommunicationInterface<'_>, ) -> Result<(), RiscvError>

Configure the target to stop code execution after a reset. After this, the core will halt when it comes out of reset.

Source

fn reset_catch_clear( &self, interface: &mut RiscvCommunicationInterface<'_>, ) -> Result<(), RiscvError>

Free hardware resources allocated by ResetCatchSet.

Source

fn reset_system_and_halt( &self, interface: &mut RiscvCommunicationInterface<'_>, timeout: Duration, ) -> Result<(), Error>

Executes a system-wide reset without debug domain (or warm-reset that preserves debug connection) via software mechanisms.

Implementors§