Struct stm32_metapac::pwr::Pwr
pub struct Pwr { /* private fields */ }
Expand description
PWR
Implementations§
§impl Pwr
impl Pwr
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self
pub const fn as_ptr(&self) -> *mut ()
pub const fn cr2(self) -> Reg<Cr2, RW>
pub const fn cr2(self) -> Reg<Cr2, RW>
This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.
pub const fn cr3(self) -> Reg<Cr3, RW>
pub const fn cr3(self) -> Reg<Cr3, RW>
Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.
pub const fn d3cr(self) -> Reg<D3cr, RW>
pub const fn d3cr(self) -> Reg<D3cr, RW>
This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software
pub const fn wkupcr(self) -> Reg<Wkupcr, RW>
pub const fn wkupcr(self) -> Reg<Wkupcr, RW>
reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).