Struct cortex_m::peripheral::SCB

pub struct SCB { /* fields omitted */ }

System Control Block

Implementations

impl SCB

pub fn vect_active() -> VectActive

Returns the active exception number

impl SCB

pub fn enable_icache(&mut self)

Enables I-Cache if currently disabled

pub fn disable_icache(&mut self)

Disables I-Cache if currently enabled

pub fn icache_enabled() -> bool

Returns whether the I-Cache is currently enabled

pub fn invalidate_icache(&mut self)

Invalidates I-Cache

pub fn enable_dcache(&mut self, cpuid: &mut CPUID)

Enables D-cache if currently disabled

pub fn disable_dcache(&mut self, cpuid: &mut CPUID)

Disables D-cache if currently enabled

pub fn dcache_enabled() -> bool

Returns whether the D-Cache is currently enabled

pub fn clean_dcache(&mut self, cpuid: &mut CPUID)

Cleans D-cache

pub fn clean_invalidate_dcache(&mut self, cpuid: &mut CPUID)

Cleans and invalidates D-cache

pub fn invalidate_dcache_by_address(&mut self, addr: usize, size: usize)

Invalidates D-cache by address

addr: the address to invalidate size: size of the memory block, in number of bytes

Invalidates cache starting from the lowest 32-byte aligned address represented by addr, in blocks of 32 bytes until at least size bytes have been invalidated.

pub fn clean_dcache_by_address(&mut self, addr: usize, size: usize)

Cleans D-cache by address

addr: the address to clean size: size of the memory block, in number of bytes

Cleans cache starting from the lowest 32-byte aligned address represented by addr, in blocks of 32 bytes until at least size bytes have been cleaned.

pub fn clean_invalidate_dcache_by_address(&mut self, addr: usize, size: usize)

Cleans and invalidates D-cache by address

addr: the address to clean and invalidate size: size of the memory block, in number of bytes

Cleans and invalidates cache starting from the lowest 32-byte aligned address represented by addr, in blocks of 32 bytes until at least size bytes have been cleaned and invalidated.

impl SCB

pub fn set_sleepdeep(&mut self)

Set the SLEEPDEEP bit in the SCR register

pub fn clear_sleepdeep(&mut self)

Clear the SLEEPDEEP bit in the SCR register

impl SCB

pub fn system_reset(&mut self) -> !

Initiate a system reset request to reset the MCU

impl SCB

pub fn set_pendsv()

Set the PENDSVSET bit in the ICSR register which will pend the PendSV interrupt

pub fn is_pendsv_pending() -> bool

Check if PENDSVSET bit in the ICSR register is set meaning PendSV interrupt is pending

pub fn clear_pendsv()

Set the PENDSVCLR bit in the ICSR register which will clear a pending PendSV interrupt

pub fn set_pendst()

Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt

pub fn is_pendst_pending() -> bool

Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending

pub fn clear_pendst()

Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt

impl SCB

pub fn get_priority(system_handler: SystemHandler) -> u8

Returns the hardware priority of system_handler

NOTE: Hardware priority does not exactly match logical priority levels. See NVIC.get_priority for more details.

pub unsafe fn set_priority(&mut self, system_handler: SystemHandler, prio: u8)

Sets the hardware priority of system_handler to prio

NOTE: Hardware priority does not exactly match logical priority levels. See NVIC.get_priority for more details.

On ARMv6-M, updating a system handler priority requires a read-modify-write operation. On ARMv7-M, the operation is performed in a single, atomic write operation.

Unsafety

Changing priority levels can break priority-based critical sections (see register::basepri) and compromise memory safety.

impl SCB

pub fn ptr() -> *const RegisterBlock

Returns a pointer to the register block

Trait Implementations

impl Deref for SCB

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for SCB